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Forum: FPGA, VHDL & Verilog HELP on understanding .tcl file.


Author: Karthiga G. (karthiga05)
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Hi everyone. I need to understand these following 3 lines from my .tcl 
file. Can someone please explain them to me? Thanks in advance!
read_netlist /MicroE/microe01/units/AUDIO/HVT/final_hvt.v  -top ml_classifier_chip
read_sdc /MicroE/microe01/units/AUDIO/HVT/final_hvt.sdc


read_vcd -vcd_module top_inst -module ml_classifier_chip /MicroE/microe01/units/AUDIO/HVT/compute.vcd 

# read_vcd -activity_profile -time_window 10000 -simvision -vcd_module top_inst -module ml_classifier_chip /MicroE/microe01/units/AUDIO/HVT/compute.vcd 

# read_vcd -vcd_module ml_classifier_chip -module ml_classifier_chip -start_time 0 -end_time 141606000 /nypdata04/digital/digit_02/projects/Audio/RC/init.vcd

report power > $resultsDir/final_power_hvt.rpt
report gates > $resultsDir/final_gates_hvt.rpt

Author: Duke Scarring (Guest)
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Maybe your 3 is not my 3, I see seven lines of code...

All lines call program specific tcl functions: read_netlist, read_sdc, 
read_vcd, report
Take a look in your application manual to get an explanation for this 
functions.

Duke

Author: Karthiga G. (karthiga05)
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Duke Scarring wrote:
> Maybe your 3 is not my 3, I see seven lines of code...
>
> All lines call program specific tcl functions: read_netlist, read_sdc,
> read_vcd, report
> Take a look in your application manual to get an explanation for this
> functions.
>
> Duke

oops. i forgot to bold them. sry.

Author: Karthiga G. (karthiga05)
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so basically its just reading the files?

Author: Karthiga G. (karthiga05)
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Also could you explain to me what is top-level module?

Author: Karthiga G. (karthiga05)
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what im doing now is actually Power Analysis. So why do i have to read 
the netlist and sdc file when a vcd file should be enough to determine 
the power?

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