Forum: FPGA, VHDL & Verilog URGENT! Gate-lvel Netlist

Author: Karthiga G. (karthiga05)
Posted on:

Rate this post
0 useful
not useful
Hi. Can someone please help me explain what is gate-level netlist and 
what is it used for? urgently need it. thanks!

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
A gate-level netlist contains only LUTs and FlipFlops (in case of an 
FPGA) the basic chip elements. You can use it for timing simulation or 
to check the synthesiser result.
If you have an strictly synchronous design, you can skip this kind of 
simulation normally.



Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.