Hi. Can someone please help me explain what is gate-level netlist and what is it used for? urgently need it. thanks!
A gate-level netlist contains only LUTs and FlipFlops (in case of an FPGA) the basic chip elements. You can use it for timing simulation or to check the synthesiser result. If you have an strictly synchronous design, you can skip this kind of simulation normally. Duke
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.