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Forum: FPGA, VHDL & Verilog How to initialize the memory in testbench when simulate a processor ?


Author: Min Peter (Company: NUDT) (peter_123)
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Hi, everyone!

In my project, I use a procedure "file sim_vector  in stimulation.txt" 
in the textio lib to read the stimulation file into "sim_vector", and 
then I read the file line by line. In each line , I read the stimulating 
data one by one, and put them one by one into the right port of the 
memory(ram).

I think it too slow to input the program and data into the ram, and a 
little bit complicated.


What I need is a procedure or method in VHDL, just like 
"readmemb<memory, stimu.txt, @address>" in verilog, to inital my ram . 
So could u help me?

Author: user (Guest)
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you can use your function to write direct to the memory

type array(1024 downto 0) of std_logic_vector(31 downto 0);
signal memory : myarray := init_function("filename");

you only need to write a inif_function, which returns an array with the 
memory content

Author: Min Peter (Company: NUDT) (peter_123)
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Thank you!!^_^

Author: Min Peter (Company: NUDT) (peter_123)
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I write a sram.vhd, and ues a tb_sram.vhd to simulate the sram. So, the 
initial_function() should be write in the sram.vhd, or the tb_sram.vhd?

Author: Duke Scarring (Guest)
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The initial_functionl() go to sram.vhd
If you synthesize your design for a FPGA target the memory will be 
filled on startup with your program to.

Duke

Author: Min Peter (Company: NUDT) (peter_123)
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hi!
you mean that I should design the init_function(stimulation.txt) in my 
sram.vhd?
I wanna use: [file stimulation_file : text is in  "stimulation.txt"] , 
when I design the function, then read the stimulation_file line by line, 
and put the value into each unit of my sram, so am I right?

Author: Duke Scarring (Guest)
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> so am I right
Yes. Take a look at:

http://tams-www.informatik.uni-hamburg.de/vhdl/mod...

(and try to use ieee.numeric_std.all instead...)

Duke

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