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Forum: FPGA, VHDL & Verilog Nested if rising_edge(clk) statements?


Author: Anthony (Guest)
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I've come across this in some code, and I'm really curious what it does:

if rising_edge(clk) THEN

   --do some flip flop things

   if rising_edge(clk)THEN

      --do other flip flop things
   end if;
end if;

Does this code make it take 2 rising edges to get to the "inner" if 
statement? or is the second if statement completely redundant?

Thanks, any help is appreciated.

Author: user (Guest)
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the second statement, reacts on the same condition, so it is redundant 
and can be removed

Author: user2 (Guest)
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No this wait-statement cannot be just removed because it is in no wy 
redundant. The simulator awaits there the next rising edge to process 
the next few statements.
The resulting hardware realisation depends on your specific synthesiser. 
It is not unlikely that this is not synthesisable, too.

Author: user2 (Guest)
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Ah, sorry, I am just a bit too tired and read an wait until instead of 
an if.. then.
You are right, of course!

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