Forum: FPGA, VHDL & Verilog <= and => operators

Author: superzanti (Guest)
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What is the difference between the => operator and the <= operator. I 
can't figure it out. i thought they were both signal assignment 
operators for the longest time.

Thank you.

Author: hhhh (Guest)
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Hi, the following statement maybe not a full declaration but for 

the <= operator assigns signals from the right to the left signal

the => operator maps signals e.g. inner signals to outter signals, 
furthermore the => operator is used in switch-case structures and to map 
single bits of a vector (0 => '1', 1 => '0', others => '0'), which means 
bit 0 of the vector should be HIGH, bit 1 should be LOW and all other 
bits should be LOW


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