hello, I'm currently working on a component that has the following behavior: 1) control component: ENTITY CONTROL IS GENERIC (FILE_NUMBER: NATURAL: = 10); PORT (FINISHED: IN STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0); CLK: IN std_logic; RST: IN std_logic; ENABLE: OUT STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0)); END CONTROL; 1.1 - Has the function of signaling which file must be read. It indicates that through a bit of door ENABLE. 1.2 - when the file finished being read, it indicates through a bit of door FINISHED. 1.3 - The control then passes to another file and repeat 1 and 2 until no more files to be read. ------------------------- 2) component of the reading of files ENTITY IS ARQ_MOD GENERIC (DATA_SIZE: NATURAL: = 16); PORT (ENABLE: IN std_logic; FINISHED: OUT std_logic; OUTPUT_DATA: OUT STD_LOGIC_VECTOR ((DATA_SIZE - 1) downto 0)); ARQ_MOD END; 1.1 - Has the function to open a file when the door ENABLE = '1 '. 1.2 - Read the file until the end. 1.3 - FINISHED = '1 '. indicates that the file over. 1.4 - OUTPUT_DATA = 'Z'. because the modules file are all connected to a bus. -------------------------------- need help on the following issues: * A plan to use a control unit and connect a number N of modules file to this control unit, for example using a LOOP GENERATE. the output of them was connected to a single bus. When ENABLE = '0 '-> OUTPUT_DATA =' Z ', then only the module in use has possession of the bus. * I would like to know how to pass the path of the file to file_open dynamically. * also, i need some ideas of implementation.... here is the idea of the circuit. http://www.photoshop.com/users/masx/...b35e3090d4c66c thanks.
Hello, I´m new in VHDl Programming , i´m using a altera FPGA ... i need to read the velocity from a dc motor to use a PID control. Could some one help me how to do it?
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