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Forum: FPGA, VHDL & Verilog continuous wavelet transform with VHDL


Author: Yahya (Guest)
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I need to build a continuous wavelet transform with VHDL using complex 
Morlet wavelet. I don't know how to deal with this algorithm and how to 
deal with the heavy convolution process at each scale.

I know that I can do that easily by Matlab, but please if any one can 
help me doing that in VHDL.
Thanks

Yahya

Author: Br ian (brian_w17)
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Your best bet is going to be to try and find some good IP cores. The 
brute of the project will likely be interfacing and learning how to use 
the cores.

The convolution for each scale factor can probably be realized using an 
FIR core. Check out Xilinx for free ones! You don't have to worry about 
computation load of convolution though.... its not like a processor. You 
can do as much as you want in parallel. You can probably calculate the 
outputs of each scale factor at the same time and sum them at the end! 
I'm no wavelet expert though.

Sysgen might be useful for you as well.

In general, if you're not acquainted with FPGA land (or perhaps even if 
you are!), this is not going to be an easy project. IMO, this is 
masters-thesis level work or above.

Author: Yahya (Guest)
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Hi Brian,

Thanks for your comments, really I am PhD student, and the cwt processor 
is a part of my thesis.

What do you think on working on the HDL- coder provided by Matlab for 
building the system? is it helpful?

I have previous FPGA knowledge, but such system is very complex if built 
by hand written HDL.

So, as you said, searching on some ip cores is much better.

I am thinking on doing cwt by fft to reduce computationd, while it is 
also not an easy task.

The xilinx ip cores doesn't support all of the FPGA families.

Regards
Yahya

Author: Br ian (brian_w17)
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Hello Yahya

Ahh that makes sense :)

I can't speak to the generic Simulink HDL coder, as I have not 
personally used it. The Xilinx blocks in Sysgen/simulink should produce 
synthesizable code, though.

What device are you targeting?

You may want to check out opencores.com. They have some free DSP cores 
that may be useful for you.

I'd expect that most FPGA vendors will have very flexible FFT cores you 
can use.

Really, If you have FPGA experience, working at the IP core level 
shouldn't be too bad if you have to do HDL. Interfacing to DSP cores 
usually isn't too difficult unless you start using some of the more 
elaborate configurations.

Is this for a real-time system?

Author: Yahya Qassim (Company: Griffith uni) (yahyataher)
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Hi Brian,

I will check the open cores, thanks for that.

My target is Spartan 3AN1400 included within Altium 3000 FPGA kit.

I supposed to built a real time system, while it is not an easy task, 
but I will start work on that.

Also, I will investigate the ability of system generator.
As you said, working on existed cores is much better than buiding hand 
written HDL code, especially in complex tasks.

I  hope that I can acheive something.

Author: Br ian (brian_w17)
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Hello Yahya

I randomly came across something the other day when looking through the 
ISE install.

So, in the sysgen install directory, there are a bunch of example 
designs. It may be worth your time to spend a half hour or so browsing 
those files. I saw a few wavelet implementations in SysGen that might be 
useful for you. I only recall DWT... but i didn't look through the whole 
thing, so there may be a CWT too.

Good luck!

Author: Yahya (Guest)
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Hi Brian

Thank you for that. But sure you mean 2011 system gen. version.
The one that I have is 2008.

So, I will check the recent pdfs for system generator.

Regards

Author: M.K. (Guest)
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would you recommend to shun Sg an do such things in plain VHDL?

It appears to me, that more and more such cores can be found totally 
ready built.

Author: Br ian (brian_w17)
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In my opinion, I would say that it is somewhat based on personal 
preference.

Personally, I have never been a huge fan of simulink (probably because 
i'm just not very experiened with it :P ) and learning SysGen is no 
trivial task, especially for a complex project like this. But then on 
the other hand, living at that level of abstraction makes a lot of 
things MUCH easier if you understand how to configure things properly. 
That and HW co-sim is pretty awesome :)

And, as you mentioned, with all the cores out there, it probably 
wouldn't be much more difficult to code it up. Just depends on what your 
experience level is with HDL vs. Simulink/SysGen and what the 
specifications are for the target project.

That's just my $.02. I'm sure others will have their opinions.

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