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Forum: FPGA, VHDL & Verilog Need serious help here! VHDL


Author: yappy yap (Company: suntet) (vhdlvhdl)
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Hi! I'm new to VHDL and have been trying to learn it for the past 
2weeks,
i would like to ask for help for my project, which is Development of 
Universal Asynchronous Receiver Transmitter (UART) using VHDL.
I have drawn the board diagram , and the expected wave form for my 
project, but is facing trouble coding it. I have attached my pictures of 
'board diagram and waveform' in the attached files, hope u all can help 
me out.
i have try coding the clock divider,
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_unsigned.all;

entity divider is
port (clk: in std_logic;
    output_clk, output_clk2: out std_logic);

end;

architecture sim of divider is

    signal count: integer range 0 to 250000;
    signal reg: std_logic;
    signal count2: integer range 0 to 868056;
    signal reg2: std_logic;

begin

output_clk <= reg;
output_clk2 <= reg2;

process(clk)
begin


        if rising_edge(clk) then

        if (count < 249999) then
            count <= count + 1;
        else
            count <= 0;
       end if;

       if (count < 125000) then
           reg <= '0';
        else
           reg <= '1';
       end if;

       if (count2 < 868055) then
           count2 <= count2 + 1;
        else
           count2 <= 0;
    end if;
       if (count2 < 434028) then
            reg2 <= '0';
            else
            reg2 <= '1';
        end if;

     end if;

end process;
end;
and also the ring counter,

Library IEEE;
Use IEEE.std_logic_1164.all;

entity ring is port
(clk, reset : in std_logic;
 G1, G2, G3, G4 : out std_logic);
end;

architecture ring_counter of ring is
        signal reg1, reg2, reg3, reg4: std_logic;

begin
    G1 <= reg1;
    G2 <= reg2;
    G3 <= reg3;
    G4 <= reg4;

 process (clk, reset)
    begin
    if (reset='0') then
        reg1 <= '0';
        reg2 <= '1';
        reg3 <= '1';
        reg4 <= '1';
elsif (clk'event and clk='1') then
            reg4 <= reg1;
            reg3 <= reg4;
            reg2 <= reg3;
            reg1 <= reg2;
    end if;
end process;
end;

please feel free to guide me on the other blocks,
Thanks!

Author: Lothar Miller (lkmiller) (Moderator)
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You should not work with "divided" clocks, but with clock enables.
That means: you have only 1 clock in the hole design. This is the 
crystal connected to your fpga. And you only generate clock enables that 
are valid for one cycle of this "master" clock.

So, its like this:
process(clk)
begin
   if rising_edge(clk) then

        if (count1 = 249999) then
           count1 <= 0;
           ce1 <= '1';
        else
           count1 <= count1 + 1;
           ce1 <= '0';
       end if;

       if (count2 = 868055) then
           count2 <= 0;
           ce2 <= '1';
        else
           count2 <= count2 + 1;
           ce2 <= '0';
      end if;
  end if;

end process;

-- using the clock enables:
process(clk)
begin
   if rising_edge(clk) then

        if (ce1 = '1') then
             -- do st once each 250000 cycles
        end if;

       if (ce2 = '1') then
             -- do st once each 868056 cycles
       end if;
  end if;

end process;

Your ring is just an ordinary shift-register. I would do it this way:
Library IEEE;
Use IEEE.std_logic_1164.all;

entity ring is port
(clk, reset : in std_logic;                           -- why do you need a reset?
 G1, G2, G3, G4 : out std_logic);                     -- why not using a vector like    G : out std_logic_vector(3 downto 0);
end;

architecture ring_counter of ring is
signal sr: std_logic_vector(3 downto 0) := "0111";    -- when you can use default values

begin
   G1 <= sr(0);
   G2 <= sr(1);
   G3 <= sr(2);
   G4 <= sr(3);
   sr <= sr(0) & sr(3 downto 1) when rising_edge(clk);
end;


Debouncing is also a shift register
(btw: most of the world is a shift register...:-)
Library IEEE;
Use IEEE.std_logic_1164.all;

entity debounce is port
(clk          : in std_logic;     -- no need for a reset !!!
 ce200hz      : in std_logic;     -- a clock enable with 200 Hz
 transmit     : in std_logic;  
 transmit_int : out std_logic);
end;

architecture behave of debounce is
signal sr: std_logic_vector(2 downto 0) := "000";  
begin
   sr <= sr(1) & sr(0) &  when rising_edge(clk);
   process(clk) begin
     if rising_edge(clk) then
        if (ce200Hz = '1') then   -- shift in new input level
             sr <= sr(1) & sr(0) &  transmit;
        end if;
        if (sr = "110") then      -- falling edge
             transmit_int <= '1';
        else
             transmit_int <= '0';
        end if;
     end if;
   end process;
end behave ;



BTW:
   if (count < 249999) then
       count <= count + 1;
   else
       count <= 0;
   end if;
This counts 1 to much: from 0 to 250000 are 250001 clock cycles...  :-o

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