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Forum: FPGA, VHDL & Verilog On-chip communication protocol like AMBA AHB


Author: Mido11 (Guest)
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Hi all,

I have some difficulty by understanding the reason why only one master 
can own the bus system at the time even if another master do not want to 
access the same target which responds the first master request.

which penalty shall the bus to face if it is suitable to deal with this 
option?

Thanks
Mido

Author: Marcus Harnisch (mharnisch)
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Mido11 wrote:
> I have some difficulty by understanding the reason why only one master
> can own the bus system at the time even if another master do not want to
> access the same target which responds the first master request.

Because that is how single-layer bus systems work. Historically a bus
was a shared medium -- a piece of wire used for both, reading
and writing data. Although AHB was never meant to used in such context
(bidirectional), it still implements some of the ideas which help keep
the area at a minimum. Nowadays, where silicon area isn't as much of
an issue, AHB has been superceeded by multi-layer AHB(-Lite) and AXI 
fabrics.

> which penalty shall the bus to face if it is suitable to deal with this
> option?

See above.

--
Marcus

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