EmbDev.net

Forum: FPGA, VHDL & Verilog 8X8 multiplier testbench problem (ISIM)


Author: Kelvin Lau (Company: student) (jasper12)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hi , can you tell me why im getting UUUUUUUU for first value of 
product...and it seems like all the values of product are shifted 
right..... is it something to do with the clock? ive attached the 
testbench coding and simulation. THanks! :D

Author: Na sowas (Guest)
Posted on:

Rate this post
0 useful
not useful
Maybe theres a kind of problem in your COMPONENT mult8X8... :-/

Attach this file for a closer look.
(pls with extension *.vhd, and you will see some syntax highlighting 
magic)


BTW: do you know, that VHDL has a multiplcation operator, the '*'?

Author: Kelvin Lau (Company: student) (jasper12)
Posted on:
Attached files:

Rate this post
0 useful
not useful
the previous two attached files are the same..

Author: Na sowas (Guest)
Posted on:

Rate this post
0 useful
not useful
There are no previously attached files...  :-/
At least I didn't find any.

However:
This is your "problem"
     when 17 =>    
         if (A(7) xor B(7)) = '1' then      
           product <= not ACC(15 downto 0) + '1';
You assign the final value after 17 clocks. So until then the result is 
-U-ndefined.

A solution for you is to assign a default value to Product like this:
entity mult8X8 is
        port (Clk, St: in std_logic;
            Mplier,Mcand : in std_logic_vector(7 downto 0);
            Product: out std_logic_vector(15 downto 0) := (others => '0'); -- some little magic here
            Done: out std_logic);
end mult8X8;


BTW: do you know, that VHDL has a multiplication operator, the '*'?
So you could smply write: Product <= Mplier * Mcand;

Author: Kelvin Lau (Company: student) (jasper12)
Posted on:

Rate this post
0 useful
not useful
It worked. THanks!

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.