Hi , can you tell me why im getting UUUUUUUU for first value of product...and it seems like all the values of product are shifted right..... is it something to do with the clock? ive attached the testbench coding and simulation. THanks! :D
Maybe theres a kind of problem in your COMPONENT mult8X8... :-/ Attach this file for a closer look. (pls with extension *.vhd, and you will see some syntax highlighting magic) BTW: do you know, that VHDL has a multiplcation operator, the '*'?
There are no previously attached files... :-/ At least I didn't find any. However: This is your "problem"
1 | when 17 => |
2 | if (A(7) xor B(7)) = '1' then |
3 | product <= not ACC(15 downto 0) + '1'; |
You assign the final value after 17 clocks. So until then the result is -U-ndefined. A solution for you is to assign a default value to Product like this:
1 | entity mult8X8 is |
2 | port (Clk, St: in std_logic; |
3 | Mplier,Mcand : in std_logic_vector(7 downto 0); |
4 | Product: out std_logic_vector(15 downto 0) := (others => '0'); -- some little magic here |
5 | Done: out std_logic); |
6 | end mult8X8; |
BTW: do you know, that VHDL has a multiplication operator, the '*'? So you could smply write: Product <= Mplier * Mcand;
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