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Forum: FPGA, VHDL & Verilog multiple driver error


Author: rajendra soloni (Company: bvb) (soloni)
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hi all,


I am getting multiple driver error in my vhdl program.So pls help me.

My program is to connect two rams to processor put data into rams 
through processor then disconnect them from processor.Then do the 
operation with data present in rams and processor should read the 
result.is there otherway to do this project.

I am using xilinx 12.2 tool.

I am attaching the code getting errors so pls help me..

errors are:

Error:XST:528:Multi-source in Unit<procint> on signal 
<Mcount_adresss_cy<0>>; this signal is connected to multiple drivers.

Author: Na sowas (Guest)
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This error means: you are driving (at least) this signal from more than 
(at least) one process. Or you are driving this signal from a process 
and a concurrent statement...

The problem in your code is addresss, its driven from 2 processes.

But there are al lot of more problems to come!!!
Lots of them are reported in the warnings. This are at least highest 
warning level, maybe this should be an error:
WARNING:Xst:737 - Found 1-bit latch for signal <s1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <done>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <addresss>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Author: Na sowas (Guest)
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BTW:
process (done) -- sensitivity list is incomplete: clk is missing
  begin
    if done='1' then
       if (clk'event and clk='1') then
         if (en = '1' and rd='1' and wr='1' and s2='1' and count1="111" and s1='0' ) then ...
Due to the incomplete sensitivity list your simnulation ist totally 
crap.
And the description of an asynchronous clock enable is very unusual... 
:-/

This warning is also a very high level warning:
 Index value(s) does not match array range, simulation mismatch.
It simply says: you're not simulating the actual hardware...

Author: soloni (Guest)
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hi, thanks for suggestion.
i have used the clk in sensitivity list and also checked with other 
signals
s2,wr,en,rd but getting same warnings.
Please suggest me what to do for that multiple error.

Author: Na sowas (Guest)
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> i have used the clk in sensitivity list and also checked with other
> signals s2,wr,en,rd but getting same warnings.
This incomplete sensitivity list does not cause your problems!
Its just another problem.

> Please suggest me what to do for that multiple error.
Don't assign values from more than 1 process to a signal. I already said 
tis:
>>> This error means: you are driving (at least) this signal from more
>>> than (at least) one process.
>>> The problem in your code is addresss, its driven from 2 processes.

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