Forum: FPGA, VHDL & Verilog asynchronous_delay

Author: Wolfgang Lammer (Company: ims) (asciwolli)
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I need to implement a strobe-signal-delay of 2ns in the output-path
to get the optimal point in time for clocking an external
chip over a delayed data-path. (FPGA: LatticexP2-family, there are no 
and a have no PLL anymore)

Implementation as synchronous-logic would lead to clk-freuqency of 

Is it possible to work around by instantiatig dedicated 
entities to utilise the delay, ore/and making some constraints.... ?

Author: Ottmar (Guest)
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There are always two ways to adjust small delays.

1. Adding logic or delay elements either in rtl description (make sure 
that synthesis do not optimize away) or by instantiation of library 
cells from your FPGA. Some FPGA technologies has dedicated delay 

2. Routing. Move logic elements in the path in a way that the routing 
length increase. That need much trial and error, because you have usally 
no real influence to the routing.

2a. Routing add I/O. do not use the FF in the I/O cell and you will get 
additional delay.

Be aware, you have to check the timing at least at best and worst case 


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