Posted on:
Hello, i'm new to ARM7 and i'm trying to build a application using freertos and an interrupt driven uart (uart0 in my case). Unfortunately the isr is not called (THRE and RX). But if i set VICSoftInt the ISR is called.
VICSoftInt = 0x40; |
Can anyone point me to a probable cause? Did imiss setting a certain register? I use the current codesourcery toolchain for linux. UART init:
/* Constants to setup and access the UART. */ #define serDLAB ( ( unsigned char ) 0x80 ) #define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 ) #define serNO_PARITY ( ( unsigned char ) 0x00 ) #define ser1_STOP_BIT ( ( unsigned char ) 0x00 ) #define ser8_BIT_CHARS ( ( unsigned char ) 0x03 ) #define serFIFO_ON ( ( unsigned char ) 0x01 ) #define serCLEAR_FIFO ( ( unsigned char ) 0x06 ) #define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 ) /* Constants to setup and access the VIC. */ #define serUART0_VIC_CHANNEL ( ( unsigned long ) 0x0006 ) #define serUART0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 ) #define serUART0_VIC_ENABLE ( ( unsigned long ) 0x0020 ) void init() { ............. /* Setup the baud rate: Calculate the divisor value. */ ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING * 4; // * 4 because of PCLK_UART0 ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; /* Set the DLAB bit so we can access the divisor. */ U0LCR |= serDLAB; /* Setup the divisor. */ U0DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff ); ulDivisor >>= 8; U0DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff ); /* Turn on the FIFO's and clear the buffers. */ U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); /* Setup transmission format. */ U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; /* Enable UART0 interrupts. */ U0IER = serENABLE_INTERRUPTS; //RBR and THR IRQ /* initialize VIC */ VICIntEnClr = 0xffffffff; VICVectAddr = 0x00000000; VICIntSelect = 0x00000000; /* all IRQ */ /* Setup the VIC for the UART. */ VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT ); //IRQ, not FIQ VICIntEnClr = serUART0_VIC_CHANNEL_BIT; VICVectAddr6 = ( long ) vUART_ISR_Handler; VICVectCntl6 = 0xF; //Prio VICIntEnable |= serUART0_VIC_CHANNEL_BIT; .......... } |
Posted on:
IRQs enabled on core-level? See core documentation: CPSR, I-Bit.
Posted on:
Hi Martin, thank you. I will have a look at the core documentation. The CPSR access is handled by freertos. I will ad some debug code and hope that i find the problem.
Posted on:
Now the ISR is responding. I made some mistakes in the freertos configuration (stack too small and one queue was too big). The ISR works, the ticks work, but receiving characters from the serial queue does not work yet.
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