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VHDL records
von Mark G. (Company: JHU Applied Physics Lab) (mwgilson)

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I am trying to figure out if it is possible to assign all contents of a 
record with a single statement or assign an output port as the entirety 
of a record...for example:

Declarations & signal creation...etc...
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type MY_RECORD is record

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    A : std_logic;

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    B : std_logic;

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    C : std_logic_vector(5 downto 0);

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    D : std_logic_vector(8 downto 0);

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    E : std_logic_vector(14 downto 0);

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  end record;

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signal my_new_rec : MY_RECORD;

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 process (SYSCLK, nRESET) is

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  begin

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    if nRESET = '0' then

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      my_new_rec  <= (others => '0');

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 ...

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...

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PORT_OUT  <= my_new_rec;


I've tried the .ALL (e.g. my_new_rec.ALL) but that is of course used 
with variables.  Then I began to wonder if it might be possible to 
complete this task by using variables as an intermediate?  If anyone has 
any ideas please let me know.  In short, I'm trying to use records to 
further subdivide a 32 bit std_logic_vector so I can do things like:

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if(my_new_rec.A = '1') then

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etc...

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end if;


Please help.

  


  




  

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    Re: VHDL records
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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With a default constant like this:
1
type MY_RECORD_t is record

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    A : std_logic;

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    B : std_logic;

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    C : std_logic_vector(5 downto 0);

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    D : std_logic_vector(8 downto 0);

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    E : std_logic_vector(14 downto 0);

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end record;

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constant default_my_record_c : my_record_t := (

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  a => '0',

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  b => '0',

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  c => (others => '0'),

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  d => (others => '0'),

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  e => (others => '0')

14
);

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signal my_new_rec : MY_RECORD_t;

1
 process (SYSCLK, nRESET) is

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  begin

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    if nRESET = '0' then

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      my_new_rec  <= default_my_record_c;

5
 ...

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...

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PORT_OUT  <= my_new_rec;


Duke

  


  




  

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    Re: VHDL records
  


  

    

      von
      
        Andreas S.
        (andreas)
        (Admin)
      
      


      
    


    

      
    

    

    

  
  


  

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You can't use records to directly subdivide a vector. If you want to use 
a record, you need to assign the components manually (or write a 
function to do it). Another option is using aliases:

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alias a is my_slv(5);

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alias b is my_slv(4 downto 0);

3
4
if (a = '1') then

5
...

6
end if;


  


  




  

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    Re: VHDL records
  


  

    

      von
      
        Mark G.
            (Company: JHU Applied Physics Lab)
        (mwgilson)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Duke, I think your method is a good solution to initialize a 
record...thanks!
Andreas, I think this is one possible solution to parsing individual 
parts of a vector...but in my scenario I will have tens of these records 
of different types and I'm concerned these aliases could take up alot of 
code space.  I think what I've found is that records are not the answer 
to my problem.

To follow up, what are your suggestions to taking an input 
std_logic_vector(31 downto 0) and also an output std_logic_vector(31 
downto 0) and having the ability to dynamically "cast" these to 
particular "formats" based on a given state.  In other words, maybe at a 
given time each bit in the input std_logic_vector has a different 
"name", but in another state the input is divided into an upper and 
lower word.  instead of doing:

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alias a is input(0);

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alias b is input(1);

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alias c is input(2);

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...

5
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alias a_a is input(31 downto 16);

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alias a_b is input(15 downto 0);

8
...


I would have tens and tens if not hundreds of aliases if I did it this 
way, which is why I tried using records until I found out there 
limitations.  No other solutions?

  


  




  

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