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Hello, I'm an engineer at National Institute of Nuclear Physics - section of Catania, Italy- (INFN, Istituto Nazionale di Fisica Nucleare in Italian). we're looking for the SIMPLEST way to send data with a rate as close as possible to the Giga with the Ethernet protocol. Do you have any suggestion about the chip or the core we could use? Thanks
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Very easy, very cheap: Use a PCI-core (DMA-capable) on the FPGA and a Realtek 8169-based PCI-Network card (9Euros in single quantities or so). The 8169-series can send about 100MByte/s without problems. In fact the 8169 has the neat feature of two independent transmit queues. While the first one is handling the regular traffic of the OS, the second queue can be sourced by the FPGA with "on-demand" generated DMA descriptors. This approach is maybe not as elegant as a MAC in the FPGA. But on the other hand you can use "low"-end FPGAs. I did exactly this for UDP-streaming of DVB tuner data. If you are interested, I can give you a link to a more detailed description.
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If you are want to send close to the maximum data rate of gigabit ethernet, you will probably sending only UDP packets of one kind with predefined length and structure. In addition, you will probably use a point to point connection, so you don't really have to care about MAC and IP addresses. This means that most of the Ethernet, IP and UDP packet header bytes will be constant anyway. You will just have to provide the CRCs (and of course the data). So you can just connect a PHY to the FPGA, clock the predefined Headers, the data and the CRC (which can be calculated on the fly) to it, and you are done. Very simple hardware setup and no big black box of IP you do not understand... All information regarding packet structure can be found on Wikipedia. For CRC generators see OpenCores, for example. If you have complete control over the receiver, you could even forget UDP and drop down to raw ethernet frames, which would make the transmitter even simpler.
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Hi, I would like to know more details about implementing MAC protocol in FPGA. I am using a ProASIC PLUS FPGA. I have doubts over how to manage reflections in communication?What are the interface requirements?
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I'd like to reveal this thread. I am also focussing nearly 1GB transmission speed and like to use UDP (or possibly RAW transfer, as mentioned) but I worry about routing: I will have to send data through a switch where the PC is linked to, furthermore the PC will send some status data to the FPGA, which is used to configure it. Will such a simple protocol still work over a switch and both directions? All other members of the net are total under control, meaning I can setup their IP adresses. Collision also could by avoided of necessary, meaning, I can switch the FPGA and the PC from sending to receiving manually to do that exclusively
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Hello , i want to send data to my ethernet controller on my FPGA(cyclone) board of Altera. What algorithm of sending data via this interface ?? What first steps i need to do in order to accomplish this mission. Maybe someone can advise me some book that can help me in this project. Thanks.
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Jaromir wrote: > I'd like to reveal this thread. > > I am also focussing nearly 1GB transmission speed and like to use UDP > (or possibly RAW transfer, as mentioned) but I worry about routing: > > I will have to send data through a switch where the PC is linked to, > furthermore the PC will send some status data to the FPGA, which is used > to configure it. > > Will such a simple protocol still work over a switch and both > directions? > You need an MAC address. you need ARP address resolution protocol. This connect you Hardware(mac-address labeled) with your IP address.
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