Basically I have to do the Verilog code for a syncronic system that
detects during consecutive clock cycles either of the sequences 0110 or
01011 (written with the first bit received at the left, last bit on the
right) in the single serial input x.

The input x is 1-bit. The circuit must use a FSM of Moore's type. The
direction of the sequence must be indicated by making the output of the
circuit z be a logic 1.
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Those are the instructions (they were in Spanish, so translation may not
be perfect), all I managed to do is obtain the state diagram and table.
Problem lies that the professor is basically having us self learn
Verilog and do this homework which I dont even know how to start with.

Dont need the full code though I dont want my homework done for me, just
a hint or something to point me in the right direction so I could finish
this by myself.