This is the first time i am exposed to VHDL , and i am currently no idea
on doing my project, hopefully any expert here can help me and guide me
on doing this ,thanks in advanced.

Objectives:
· Designing, Modeling and Simulation of Traffic Light Controller using
VHDL.
· Verification of the functionality using a VHDL test bench, using
qu(at)rtus II
from Altera.
· Synthesizing the verified VHDL Model of Traffic Light Controller
specifications using synthesis tool, qu(at)rtus Integrated System (QIS)
from
Altera for structural simulation.
· Downloading the designed codes into FPGA board for verifying the
algorithm
(Traffic Light Controller) functionality.

A. Design Specifications
Traffic lights are integral part of modern life. Their proper operation
can spell the
difference between smooth flowing traffic and four-lane gridlock. Proper
operation
entails precise timing, cycling through the states correctly, and
responding to outside
inputs, like walk signals.
The controller to be designed controls the traffic lights of a busy
highway (HWY)
intersecting a side road (SRD) that has relatively lighter traffic load.
Figure 1 shows
the location of the traffic lights. Sensors at the intersection detect
the presence of cars
on the highway and side road. The Figure implies that both the highway
and side
roads offer single lanes for traffic in each direction. Both roads have
ordinary (Red,
Yellow, Green) signal lights. The intersection is fitted with a sensor.

B. Finite-state machine specifications
The traffic light controller works in the following way.
1. The lights controller makes use of car sensors at the intersection of
the side road
with the highway, to sense presence of cars.
2. The lights controller makes use of three timers: a 60 seconds timer
(T60), a 30
seconds timer (T30), and a 10 seconds timer (T10). Once a trigger signal
is applied
to a timer, the timer output is zero and becomes 1 after the programmed
time
period. For example, upon reset, the T30 timer output is '0' and will
become '1' after
30 s have elapsed and stays '1' until reset by the controller.
3. Pedestrians can use the intersection by pressing buttons and
debouncing switches.
Pedestrians will need to cross the highway only since crossing the side
road is
assured most of the time.
4. HWY lights remain green as long as there are no cars triggering the
SRD sensors.
5. When HWY lights have been green for a minimum of 60 seconds, a car on
SRD
may cause HWY lights to cycle through yellow to red states.
6. Meanwhile, SRD lights will turn green and remain green for a minimum
of 30
seconds. Further application of SRD sensors beyond the 30 seconds will
enable
SRD to remain green for a maximum of 60 seconds.
7. SRD lights will cycle through yellow and red states and HWY lights
will then turn
green.
8. The lights stay yellow for 10 seconds.
9. Each traffic post has three lights GREEN, YELLOW and RED.
10. In the default state, HWY lights show GREEN and SRD lights show RED.

C. Traffic light FSM Interface signals
The FSM to the traffic lights controller has the input signals shown in
Table 1. The
controller has the output signals shown in Table 2.

D. Requirements
In this project, you are required to design, model and simulate the
Finite-state
machine for the traffic light controller.
1. Draw the traffic-light controller as an icon indicating the I/O
control signals.
2. Draw a block diagram for the traffic lights controller indicating
clearly the main
system blocks and interface signals.
3. Draw a Mealy-style state diagram, which covers all legal state
transitions of the
machine.
4. Use a two- or three-process FSM VHDL coding style. Make sure you have
adequate and clear comments in your code.
5. Provide a table indicating all the input and output signals of the
traffic lights
controller and the traffic lights FSM.
E. Simulations
The VHDL code of traffic light controller will be simulated using
qu(at)rtus II software
from Altera. Different corner cases were tested by writing a test bench.
The sub
modules like the counter, register and multiplexer were written
separately and also
tested separately by test benches. Behavioural Simulation of modules
will be
represented in Timing waveform.
F. Synthesis
The verified VHDL modules then will be synthesized using synthesis tool,
QIS from
Altera. Structural simulations will be carried out in QIS and will be
compared with
behavioural simulations using the same test bench. You will present the
Register
Transfer Level (RTL) and Technology views of a Traffic Light Controller.

G. Downloaded into FPGA demo Board:
Finally, you will download your designed codes into the target
technology, Field
Programmable Gate Array (FPGA) to verify the Traffic Light Controller
function
with higher operating frequency. Noted that you will use FPGA board
(Version:
APEX20KE)

Figure 1, Table 1 and Table 2 in the attachment below