Forum: FPGA, VHDL & Verilog shift operation

Author: Jason Kee (Company: Myreka) (jasonkee111)
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can somebody explain the code below

input wire signed [16:0] D,
output reg signed [16:0] Q );

always @ * begin
    Q = D;
    Q = (Q >> 1) | (D[16] << 16);

1.  What is the meaning D[`16] << 16? from i understand, it shift left 
16 times of D whereby D only 1 bit due to D[16].  Am i misunderstand?

2. why it use Q and D in the statement  "Q = (Q >> 1) | (D[16] << 16);" 
since D is assigned to Q?



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