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Forum: FPGA, VHDL & Verilog why i have the error


Author: Michael Milan (Company: Uni Hannover) (babybk)
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Hi,
 i'm newbie in VHDL.
I want to creat  a output with value of a CONSTANT.
And use i the code

...................
entity dreieck_Signal is
    Port ( CLK_IN : in  STD_LOGIC; --CLK_IN = 50 MHZ
           RESET : in  STD_LOGIC;
           Dreieck_wave : out  STD_LOGIC_VECTOR(18 downto 0);
           max_count_wert : out STD_LOGIC_VECTOR(18 downto 0) := (others 
=> 0)
          );
end dreieck_Signal;

architecture Behavioral of dreieck_Signal is

signal  COUNT_UP : STD_LOGIC := '1';
signal  COUNT_DOWN : STD_LOGIC := '0';
signal   COUNTER_VAR : STD_LOGIC_VECTOR(18 downto 0):= (others => '0');
constant MAX_COUNT : STD_LOGIC_VECTOR(18 downto 0) := X"30C";
.......
max_count_wert <= MAX_COUNT;
Dreieck_wave <= COUNTER_VAR;
end Behavioral;
---------------------------
here is error:

"ERROR:HDLParsers:3384 - "Line 44. Size mismatch.  String literal 
"001100001100" is of size 12 but is expected to be of size 19."


Please help me.
Thanks you

: Moved by Admin
Author: Lothar Miller (lkmiller) (Moderator)
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> STD_LOGIC_VECTOR(18 downto 0) := X"30C";
19 Bits Vector /= 12 Bits Value

Author: Michael Milan (Company: Uni Hannover) (babybk)
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Thanks for your reply
how can i change my value to fit with my 19 bit Vector

And thanks again :D

Author: Fungo (Guest)
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STD_LOGIC_VECTOR(18 downto 0) := "000" & X"030C";

Author: Gast (Guest)
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How about fitting it to 19bit?
X"30C" is 12 bits, so just 7 more, and you got 19. --> X"0030C"

Author: Lothar Miller (lkmiller) (Moderator)
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> STD_LOGIC_VECTOR(18 downto 0) := "000" & X"030C"; -- 3 Bits + 16 Bits

Author: Lothar Miller (lkmiller) (Moderator)
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Gast schrieb:
> X"30C" is 12 bits, so just 7 more, and you got 19. --> X"0030C"
... Size mismatch. String literal "00000000001100001100" is of size 20 but is expected to be of size 19.

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