Hello everybody, I'm a tricore developer and I try to make the infineon tricore port of FreeRTOS to work. I use C::B and tricore gcc. The FreeRTOS dowloadable port (see www.freertos.org) for tricore is primarily developped for the TC1796, but I need to make it work for TC1766... Everything compiles OK, but while starting the code in the tricore simulator, a trap occurs in vIrqInit function (see code extract below). The trap class is 4 whith tin = 3 (Data Access Asynchronous Error). /* setup (clear) the vector table */ for ( uxCnt = 0; uxCnt < 8 * VEC_TABLE_LEN; uxCnt++ ) { if (uxCnt % 8 == 0) { trap here --> ( (unsigned long *) VEC_TABLE_BASE )[ uxCnt ] = 0x0000a000; } else { ( (unsigned long *) VEC_TABLE_BASE )[ uxCnt ] = 0; } } Any idea ?
Hello François Plese take care on architectural differences between TC1796 nad TC1766 specialy about size of SPRAM (48K for 96 and 16K 66 ) so be focused on the locator first. If it is not so please give me more details.
and one more being in trap read A11 register that normaly have to contain the last function address in.
Hello François, I know that different ports of freeRTOS have been initiated (Uni-Erlangen, Uni Budapest, TU Wien and University in Singapore). I am not absolute sure, but I think one of them have done already some work for TC1766. You can contact me and then I can provide you the contact persons. Bye, Mario
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