Processes are simply evaluated from top to bottom, nothing special
happening there. The state of a signal is determined by the last
assignment in a process, so if both west and south are '1', buttons_west
is "0000".

The best way to deal with unexpected behaviour is to use the simulator.
First you should write a test bench to feed your module with input
values and check the respective output values. If there is something
that doesn't work you can find out exactly what is wrong by
single-stepping through the code.

You can however not find any problem with the simulator. Only a strictly
synchronous design, i.e. a design that contains no or only clocked
storage elements (flip flops) works the same in real hardware as in the
simulator. In your code, you are describing a latch, which is an
asynchronous storage element and needs to be avoided. A latch is
generated because, if neither west, east nor south is '1', some of the
signals have to keep the value from before the process execution. The
only way to do that in hardware without a clock is a latch. If you need
that behavior, use a clocked process ("if rising_edge(clk)..."). If you
don't, give all signals default assignments at the start of the process.
Then the result of the process will only depend from its input
variables, not from the previous state of the signals, and you get a
simple logic network without latches.

Hi Martin

Sorry for my bad english.
You are watching on all 3 signals. First of all u have to think about :
* wich priority has each of the 3 signals
* can two or three signals = '1' at the same moment?

You dont use any Clk. That is not really good. Your Design-Software will
use some Latches.

I think the signals named rst1_ta  rst2_ta  load1_ta and load2_ta are
not correct assigned. Background:
1. west = '1' --> load1_ta = '1'
2. east = '1' --> load1_ta = '1' and load2_ta = '1' (Is this correct?)

I think the following code is a proper solution. But still without Clk.

btn_moved: process(west, east, south)
  begin
    if west = '1' then
      load1_ta <= '1';
      buttons_west(3) <= west;
      buttons_west(2) <= north;
      buttons_west(1) <= east;
      buttons_west(0) <= south;

    elsif east = '1' then
      load2_ta <= '1';
      buttons_east(3) <= west;
      buttons_east(2) <= north;
      buttons_east(1) <= east;
      buttons_east(0) <= south;

    else --(when the previous statements are not treu)
      rst1_ta <= south;
      rst2_ta <= south;

      load1_ta <= '0';
      load2_ta <= '0';

      buttons_west(3 downto 0) <= "0000";

      buttons_east(3 downto 0) <= "0000";
    end if;
  end process btn_moved;

Now thats the priority of the signals:
1. west
2. east
3. south or when none of the previos if-statement are true

Hopefully I thats helpfull.

Greetings

Martin