as I just started learning VHDL I still have a number of problems
getting things running.
I would like to write a generic adder which adds to input values bit by
In order to realize the generic functionality of the adder three
std_logic_vectors were introduced which contain the input and the output
(when the input was processed).
To check, if everything works correctly, I wrote a test bench. And
that's where the problems start. When running the syntax check I get an
error message telling me that n is not declared (in the section where
the signals are declared).
VHDL code of the test bench:
ENTITY adder_tb IS
architecture behaviour of adder_tb is
generic(n : integer := 4);
x : IN std_logic_vector(n-1 downto 0);
y : IN std_logic_vector(n-1 downto 0);
sum : OUT std_logic_vector(n-1 downto 0 );
cout : OUT std_logic
signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);
signal cout_sig : std_logic := '0';
uut: adder PORT MAP (
x => x_sig,
y => y_sig,
sum => sum_sig,
cout => cout_sig
Does anybody see the problem? Thanks very much in advace!!!!