EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL & string conversion


Author: Sebastian (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello embdev-Community.

I'm from Germany, but I'll do my very best in writing clean English ;)

I am developing with VHDL since a few weeks, I love this method to 
design hardware. All this time along I used the Xilinx ISE to create 
testbenches for evaluation.

But today I decided to write my own bench on a linuxbox. This was a 
little difficult, but in the end it worked.

I coded a for loop which iterates an array of pattern and stimulates my 
entity with the desired values. After that it compares the output saved 
in the array with the output of the entity.

If this doesn't match, an error-string is shown.

But I want to tweak this a little bit. It is not really helpful to see, 
that an error occures. It would be great to see, on which index of the 
pattern-array this thing happened.

But I really don't know how to convert the iterator i:
for i in pattern'range loop 
to a string in my error string.

My actual output is:
assert Q_is = patterns(i).Q
report "Q doesn't match!" severity error;

But I want something like: "Q doesn't match @ i", where i is replaced by 
it's value.

Since I only coded CPLD-Hardware for synthesizing, I'm absolutely 
unfamiliar with strings a.s.o. in VHDL.

Hope, someone could help.

Greets and best wishes from Germany,
Sebastian

Author: Matthias G. (mgottke)
Posted on:

Rate this post
0 useful
not useful
Hallo Sebastian,
so geht's:
report integer'image(i) & ": Q doesn't match!" severity error;
Viel Erfolg.

Author: Sebastian (Guest)
Posted on:

Rate this post
0 useful
not useful
Herzlichsten Dank, genau das hat mir gefehlt!

Gibt es eine Übersicht solcher Debug und Testing Anweisungen?

Grüße,
Sebastian

Author: Andreas Schwarz (andreas) (Admin) Flattr this
Posted on:

Rate this post
0 useful
not useful
Please write in English in this forum.

Author: Sebastian (Guest)
Posted on:

Rate this post
0 useful
not useful
Sorry, I wrote back in the german board, didn't mind that my post will 
appear also in the english.

I asked about a kind of list or summary with the most used debugging- 
and testing-codes in VHDL.

Greets, Sebastian

Author: Andreas Schwarz (andreas) (Admin) Flattr this
Posted on:

Rate this post
0 useful
not useful
There is not much else, just report, image and some file IO functions.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.