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Forum: ARM programming with GCC/GNU tools Does LPC2119 have a data cache?


Author: Dan Quinz (danq)
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Hello All,

I have implemented a simple library that places a reset code into RAM
and then resets the CPU by allowing the WDOG to timeout.  The intent is
for the 'main()' code to read this reset code and determine the reason
the application code had to reset the device (CAN buss error, internal
computation error, etc.).

What I have found is that if I write to the RAM location only once
before resetting the WDOG, the RAM location is not updated and I get the
wrong reset code value. If I write the same value twice in a row, then
the RAM location is updated and everything works ok.

Can anyone tell me if the LPC2119 ARM implementation is using a data
cache of some sort and if so, is there an explicit way to flush it to
RAM (instruction, register setting, etc.)?

Cheers!

Daniel Quinz, P. Eng.

Acacetus Inc.

Author: Clifford Slocombe (clifford)
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Why wouldn't you get this information from the user manual or data
sheet!?

www.nxp.com/acrobat_download/usermanuals/UM_LPC21XX_LPC22XX_2.pdf

No it has no cache.

Page 19 of the manual referenced above documents this feature. Your
solution is correct - actually a dummy write to any address will secure
the data.

All of which is my way of saying RTFM!

Clifford

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