Forum: ARM programming with GCC/GNU tools wildcards in makefile

Author: Dustin Sr (dbrazeau)
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I am having a little trouble using wildcards in my make file this is
what I have:

%.obj :  %.asm
  @echo File: $*.asm
  @$(ASM) $(ASM_FLAGS) GNU_$*.asm
  @cp GNU_$*.o $(OBJ)/$*.obj
  @rm GNU_$*.o

I have two asm files File.asm and GNU_File.asm and I only want to
compile GNU_File.asm and not File.asm.  How do I do this?



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