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Forum: ARM programming with GCC/GNU tools Interrupt latencies


Author: Μαtthias W. (matthias)
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Hi

Not a totally specific GCC question but anyway:
What interrupt latency can be expected on a SAM7A3 part for a GPIO
interrupt? I measured around 60 clock cycles (1.2µs at 48MHz). All code
is in flash.

Placing the ISR to the RAM (with _attribute_ ((long_call, section
(".fastrun")))) doesn't improve the latency. Is this a typical number of
clock cycles for the SAM7A3?

Matthias

Author: Martin Thomas (mthomas) (Moderator)
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Matthias Weisser wrote:
> Hi
>
> Not a totally specific GCC question but anyway:
> What interrupt latency can be expected on a SAM7A3 part for a GPIO
> interrupt? I measured around 60 clock cycles (1.2µs at 48MHz). All code
> is in flash.
>
> Placing the ISR to the RAM (with _attribute_ ((long_call, section
> (".fastrun")))) doesn't improve the latency. Is this a typical number of
> clock cycles for the SAM7A3?
>
> Matthias

Exception vectors and interrupt-wrapper (if any) als placed/running from
RAM?

Author: Μαtthias W. (matthias)
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Martin Thomas wrote:
> Matthias Weisser wrote:
>> Placing the ISR to the RAM (with _attribute_ ((long_call, section
>> (".fastrun")))) doesn't improve the latency. Is this a typical number of
>> clock cycles for the SAM7A3?
>>
>> Matthias
>
> Exception vectors and interrupt-wrapper (if any) als placed/running from
> RAM?

No, but that would be my next question: How to place exception vectors
and the interrupt wrappers in the RAM? I think I will need some magic in
the startup asm file.

The question is: Can the number of clock cycles reduced to about 30
clock cycles or so? What about the FIQ and the support in GCC for it? I
am quite new to the world of nonOS ARM.

Matthias

Author: Martin Thomas (mthomas) (Moderator)
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Matthias Weisser wrote:
> Martin Thomas wrote:
>> Matthias Weisser wrote:
>>> Placing the ISR to the RAM (with _attribute_ ((long_call, section
>>> (".fastrun")))) doesn't improve the latency. Is this a typical number of
>>> clock cycles for the SAM7A3?
>>>
>>> Matthias
>>
>> Exception vectors and interrupt-wrapper (if any) als placed/running from
>> RAM?
>
> No, but that would be my next question: How to place exception vectors
> and the interrupt wrappers in the RAM? I think I will need some magic in
> the startup asm file.
Not realy magic. Maybe parts from my AT91SAM7S "gamma" example can be
reused.
http://www.siwawi.arubi.uni-kl.de/avr_projects/arm...
There is also a contributed port for the SAM7A3 available from the
web-page.

> The question is: Can the number of clock cycles reduced to about 30
> clock cycles or so?
So far I have not done any measurements on this.

> What about the FIQ and the support in GCC for it?
There is GCC support for this (a function attribute) but it might be
easier to use an assembler-wrapper here too. The gamma example includes
a "FIQ-Wrapper" which has been copied from Atmel's startup-code that can
be found in various "basic*"-examples. You still waste a few cycles with
the wrapper but this can be optimized later if needed.


Martin Thomas

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