library ieee; use ieee.std_logic_1164.all; entity klokdeler_uren is generic(Distance : natural := 3600); port( clkin : in std_logic; clkout : out std_logic ); end entity klokdeler_uren; architecture behavioral of klokdeler_uren is begin -- Generation of pulse -- clkout : 1 pulse every CntrValue clocks -- process(clkin) variable cntr : integer range 0 to Distance; begin if rising_edge(clkin) then if (cntr < Distance) then cntr := cntr+1; clkout <= '0'; else cntr := 0; clkout <= '1'; end if; end if; end process; end architecture behavioral;