module demux ( add4, csel, cout);
    input   [3:0] add4;
    input         csel;  
    output [11:0] cout;

    wire [3:0] add_; // zanegowane!
    wire       cse_; // zanegowane!

    wire [11:0] out;
  
        

    assign cse_    = ~csel;
    assign add_[0] = ~add4[0];
    assign add_[1] = ~add4[1];
    assign add_[2] = ~add4[2];
    assign add_[3] = ~add4[3];

    assign out[0]  = add_[0] & add_[1] & add_[2] & add_[3] & cse_;    
    assign out[1]  = add4[0] & add_[1] & add_[2] & add_[3] & cse_;
    assign out[2]  = add_[0] & add4[1] & add_[2] & add_[3] & cse_;
    assign out[3]  = add4[0] & add4[1] & add_[2] & add_[3] & cse_;
    assign out[4]  = add_[0] & add_[1] & add4[2] & add_[3] & cse_;
    assign out[5]  = add4[0] & add_[1] & add4[2] & add_[3] & cse_;
    assign out[6]  = add_[0] & add4[1] & add4[2] & add_[3] & cse_;
    assign out[7]  = add4[0] & add4[1] & add4[2] & add_[3] & cse_;
    assign out[8]  = add_[0] & add_[1] & add_[2] & add4[3] & cse_;
    assign out[9]  = add4[0] & add_[1] & add_[2] & add4[3] & cse_;
    assign out[10] = add_[0] & add4[1] & add_[2] & add4[3] & cse_;
    assign out[11] = add4[0] & add4[1] & add_[2] & add4[3] & cse_; //*/
    
    assign cout[0]  = ~out[0];
    assign cout[1]  = ~out[1];
    assign cout[2]  = ~out[2];
    assign cout[3]  = ~out[3];
    assign cout[4]  = ~out[4];
    assign cout[5]  = ~out[5];
    assign cout[6]  = ~out[6];
    assign cout[7]  = ~out[7];
    assign cout[8]  = ~out[8];
    assign cout[9]  = ~out[9];
    assign cout[10] = ~out[10];
    assign cout[11] = ~out[11]; //*/
endmodule

// MODUŁ GŁÓWNY

module key_buff (csel, addr, cs, inp_so, so, si, si_out);
    input  wire [3:0]  addr; // wejśćie adresowania MUX4
    input  wire        csel; // wejście CS
    // 5
    output wire [11:0] cs; // sygnały CS 
    // 12
    input  wire    inp_so; // rozbicie sygnału SO na szyny
    output wire  [5:0] so;
    // 6
    input  wire  [5:0] si; // zebranie sygnału SI z szyn 
    output wire    si_out;
    // 7
    wire [5:0] cso;
    wire [5:0] csi;
    //
    wire    wirA;
    wire    wir_;

    // test only !! 
    /*
    assign cs[0] = 0; //addr[0];
    assign cs[1] = 1; //addr[1];
    assign cs[2] = 0; //addr[2];
    assign cs[3] = 1; //addr[3];
    //*/
    demux d16 ( .add4(addr), .csel(csel), .cout(cs)); 

    // rozdziekanie SO na 5 grup kl.
    
    bufif0 ( si_out, si[0], cs[0] );
    bufif0 ( si_out, si[1], cs[1] );
    bufif0 ( si_out, si[2], cs[2] );
    bufif0 ( si_out, si[3], cs[3] );
    bufif0 ( si_out, si[4], cs[4] );

    // zbieranie SI z 5-ciu grup kl.

    bufif0 ( so[0], inp_so, cs[0] );
    bufif0 ( so[1], inp_so, cs[1] );
    bufif0 ( so[2], inp_so, cs[2] );
    bufif0 ( so[3], inp_so, cs[3] );
    bufif0 ( so[4], inp_so, cs[4] );
    
    // zbieranie cs-ów dla 6-tej grupy

    assign wirA = cs[5] & cs[6] & cs[7] & cs[8] & cs[9] & cs[10] & cs[11]; assign wir_ = ~wirA;

    // pozostałe scalaki (6+1 przerwania+przyciski) jako 6-ta grupa 

    bufif0 ( so[5], inp_so, wir_ );
    bufif0 ( si_out, si[5], wir_ );
    //*/
endmodule