`timescale 1ns/1ps

module vga_sync_tb();

	reg			clk,reset;
	
	wire			hsync , vsync , video_on, p_tick;
	wire	[9:0] pixel_x, pixel_y	;
	
	vga_sync	u0(
		.clk(clk), .reset(reset),								
	   .hsync(hsync) , .vsync(vsync) , .video_on(video_on), .p_tick(p_tick),
	   .pixel_x(pixel_x), .pixel_y(pixel_y)						
	);
	
	always #20	clk	=	~clk;
	
	initial	begin
		clk	=	0;
		reset	=	1;
		#30
		reset	=	0;
	end

endmodule