--library ieee;
--use ieee.std_logic_1164.all;

entity tb is
end entity;

architecture struct of tb is
signal add1,add2,somma : bit_vector (7 downto 0);
signal riporto : bit;
	begin
	sommatore: entity work.addern
		generic map (enne=>8)
		port map(x_in=>add1, y_in=>add2, c_in=>'0',c_out=>riporto, s_out=>somma);
		
		process is
		begin	
			add1<="00000000";
			add2<="00000000";
			wait for 50 ns;
			add1<="00001100";
			add2<="11100000";
			wait for 50 ns;
			add1<="00011100";
			add2<="00011111";
			wait for 50 ns;
			add1<="00001111";
			add2<="11100000";
			wait for 50 ns;
			add1<="01111111";
			add2<="00000111";
			wait for 50 ns;
			add1<="00011100";
			add2<="00010000";
			wait for 50 ns;
			add1<="01110010";
			add2<="00000111";
			wait for 50 ns;
			add1<="00111100";
			add2<="01111100";
			wait for 50 ns;
			wait;
		end process;
end architecture;