library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClockEnableGenerator is

generic (
    DIVIDE_BY : integer := 5 -- give it a default value!
);

port (
    clk_in : in std_logic;
    clk_en_out : out std_logic;
    reset : in std_logic
);

end ClockEnableGenerator;

architecture rtl of ClockEnableGenerator is
signal counter : unsigned(3 downto 0) := (others => '0');
begin

  process(clk_in) begin
    if(rising_edge(clk_in)) then
      counter <= counter + 1;
      if to_integer(counter) = DIVIDE_BY-1 then
        counter <= (others => '0');
        clk_en_out <= '1';
      else
        clk_en_out <= '0';
      end if;
      if reset = '1' then
        counter <= (others => '0');
        clk_en_out <= '0';
      end if;
    end if;
  end process;

end architecture rtl;