library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gb_Arith_tb is
end gb_Arith_tb;

architecture sim of gb_Arith_tb is

component gb_Arith is
	port(
		A        : in  std_logic_vector(31 downto 0);
		B        : in  std_logic_vector(31 downto 0);
		Mode     : in  std_logic; -- 1: subtract, 0: add
		result   : out std_logic_vector(31 downto 0);
		overflow : out std_logic;
		carry    : out std_logic
	);
end component;

signal A        : std_logic_vector(31 downto 0);
signal B        : std_logic_vector(31 downto 0);
signal Mode     : std_logic;
signal result   : std_logic_vector(31 downto 0);
signal overflow : std_logic;
signal carry    : std_logic;

begin

inst_gb_Arith : gb_Arith
	port map(
		A        => A,
		B        => B,
		Mode     => Mode,
		result   => result,
		overflow => overflow,
		carry    => carry
	);

process begin
	A   <= std_logic_vector(to_unsigned(12,32));
	B   <= std_logic_vector(to_unsigned(8,32));
	Mode <= '0'; -- add
	wait for 1 ns;
	A   <= std_logic_vector(to_unsigned(28,32));
	B   <= std_logic_vector(to_unsigned(16,32));
	Mode <= '0'; -- add
	wait for 1 ns;
	A   <= std_logic_vector(to_unsigned(37,32));
	B   <= std_logic_vector(to_unsigned(41,32));
	Mode <= '1'; -- subtract
	wait for 1 ns;
	A   <= std_logic_vector(to_unsigned(9,32));
	B   <= std_logic_vector(to_unsigned(15,32));
	Mode <= '1'; -- subtract
	wait;
end process;

end;