module tb_counter_119;
  wire [6:0] dout;
  wire ctl_1, ctl_2;
  reg clk, rst; 
  
  initial begin
    clk = 0;
    forever #5 clk <= ~clk;
  end
  
  initial begin
    $monitor($time," rst=%d,dout=%d,ctl_1=%d,ctl_2=%d",rst,dout,ctl_1,ctl_2);
  end
  
  counter_119 c119 (.dout(dout), .ctl_1(ctl_1), .ctl_2(ctl_2), .clk(clk), .rst(rst));
  
  initial begin
    rst = 1;
    repeat(3) @(posedge clk);
    @(negedge clk) rst = 0;   
  end   
  
endmodule