library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fifo_tb is end; architecture fifo of fifo_tb is COMPONENT fifo port( data_in : in std_logic_vector(8 downto 0); data_out : out std_logic_vector(8 downto 0); wr : in std_logic; rd : in std_logic; rdinc : in std_logic; wrinc : in std_logic; clk,rst,wclr, rclr : in std_logic ); END COMPONENT fifo ; SIGNAL data_in : std_logic_vector(8 downto 0):="000000000"; SIGNAL data_out : std_logic_vector(8 downto 0):="000000000"; SIGNAL wr : std_logic := '0'; SIGNAL rd : std_logic := '0'; SIGNAL rdinc : std_logic := '0'; SIGNAL wrinc : std_logic := '0'; SIGNAL clk,rst,wclr, rclr : std_logic := '0'; begin dut : fifo PORT MAP ( data_in => data_in, data_out => data_out, clk => clk, rst => rst, wclr => wclr, rclr =>rclr, wrinc =>wrinc, rdinc =>rdinc, rd =>rd, wr =>wr ); clock : PROCESS begin wait for 1 ps; clk <= not clk; end PROCESS clock; stimulus : PROCESS begin wait for 3 ps; rd <='1'; wr <='1'; data_in <= "111111010"; wait for 6 ps; data_in <= "101011010"; rdinc <='1'; wait for 25 ps; wait for 5 ps; wait for 3 ps; data_in <= "111000010"; wait for 6 ps; data_in <= "101011010"; wait for 21 ps; data_in <= "110000010"; wait; end PROCESS stimulus; end fifo;