LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk_div IS PORT ( iCLK : IN std_logic; sclk : OUT std_logic ); END clk_div; ARCHITECTURE behave OF clk_div IS CONSTANT count : integer:=(34482759);------34482759 25000000 SIGNAL temp_clk : std_logic:='0'; BEGIN PROCESS(iCLK,temp_clk) VARIABLE div_count : integer:=(0); BEGIN IF (rising_edge(iCLK)) THEN IF (div_count < count) THEN div_count := div_count + 1; ELSE temp_clk <= not temp_clk; div_count:=0; END IF; END IF; sclk<= temp_clk; END PROCESS; END behave;