---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:00:25 05/02/2016 -- Design Name: -- Module Name: selectsig - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity select_sig is Port ( clock : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; s2 : in STD_LOGIC; sig : out STD_LOGIC_VECTOR(2 downto 0) ); end select_sig; architecture Behavioral of select_sig is begin process (clock,s0,s1,s2) begin if(clock'event and clock = '1') then if (s0='0' and s1='0' and s2='0') then sig <= "000"; elsif (s0='1' and s1='0' and s2='0') then sig <= "001"; elsif (s0='0' and s1='1' and s2='0') then sig <= "010"; elsif (s0='1' and s1='1' and s2='0') then sig <= "011"; elsif (s0='0' and s1='0' and s2='1') then sig <= "100"; else sig <= "---"; end if; end if; end process; end Behavioral;