---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:37:10 04/30/2016 -- Design Name: -- Module Name: OverallSystem - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity OverallSystem is Port ( clock : in STD_LOGIC; clear : in STD_LOGIC; sel : in STD_LOGIC; y : out STD_LOGIC ); end OverallSystem; architecture Behavioral of OverallSystem is signal freq1 : std_logic; signal freq2 : std_logic; begin chip1 : entity work.mux2to1 port map ( freq1 => freq1, freq2 => freq2, sel => sel, y => y ); chip2 : entity work.FreqDivider200Hz port map ( clock => clock, clear => clear, freq1 => freq1 ); chip3 : entity work.FreqDivider400Hz port map ( clock => clock, clear => clear, freq2 => freq2 ); end Behavioral;