library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FreqDivider200Hz is port( clock : in STD_LOGIC; -- 50 Mhz clear : in STD_LOGIC; freq1 : out STD_LOGIC ); end FreqDivider200Hz; architecture Behavioral of FreqDivider200Hz is signal adjfreq: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000000"; signal adjclock : std_logic := '0'; begin freq1 <= adjclock; countClock: process(clock,clear) begin if (clear = '1') then adjfreq <= "00000000000000000"; elsif(clock'event and clock = '1') then -- Flip a the output once every 125,000 cycles (400Hz) -- to give a 200Hz output with 50% duty cycle if (adjfreq = "11110100001001000") then adjfreq <= "00000000000000000"; if adjclock <= '0' then adjclock <= '1'; else adjclock <= '0'; end if; else adjfreq <= adjfreq+1; end if; end if; end process; end Behavioral;