library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adder_tdm is Port ( A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); Sum : out STD_LOGIC_VECTOR (31 downto 0); cin : in STD_LOGIC; cout : out STD_LOGIC; clk, res : in STD_LOGIC); end adder_tdm; architecture Behavioral of adder_tdm is component cla_nbits is generic (N : integer := 32); Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0); b : in STD_LOGIC_VECTOR (N-1 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (N-1 downto 0); cout : out STD_LOGIC); --inc : out STD_LOGIC_VECTOR (1 downto 0)); end component; component add_ctrl is port ( clk : in STD_LOGIC; res : in STD_LOGIC; selA, selB, mux_ctrl : out STD_LOGIC); end component; component mux is Generic (N : integer := 32); Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0); B : in STD_LOGIC_VECTOR (N-1 downto 0); mux_out : out STD_LOGIC_VECTOR (N-1 downto 0); sel : in STD_LOGIC); end component; signal Al, Ah, Bl, Bh : STD_LOGIC_VECTOR(15 downto 0); signal Ain, Bin : STD_LOGIC_VECTOR(15 downto 0); signal selA_sig, selB_sig : STD_LOGIC; signal cout_fdbk : STD_LOGIC; signal mux_out_sig, mux_out, sel_sig : STD_LOGIC; signal sum_out : STD_LOGIC_VECTOR(15 downto 0); begin Al <= A(15 downto 0); Ah <= A(31 downto 16); Bl <= B(15 downto 0); Bh <= B(31 downto 16); --sel_sig <= mux_ctrl; mux_out_sig <=mux_out; mux_A: mux generic map(N => 16) port map(A => Al, B=>Ah, mux_out => Ain, sel => selA_sig); mux_B: mux generic map(N => 16) port map(A => Bl, B=>Bh, mux_out => Bin, sel => selB_sig); cla_32: cla_nbits generic map (N => 16) Port map ( a => Ain, b=> Bin, cin => mux_out, sum => sum_out, cout => cout_fdbk); --inc : out STD_LOGIC_VECTOR (1 downto 0)); mux_onebit: process(cin, cout_fdbk, sel_sig) begin case sel_sig is when '0' => mux_out <= cin; when '1' => mux_out <= cout_fdbk; when others => mux_out <= '0'; end case; end process mux_onebit; ctrl: add_ctrl port map( clk => clk, res => '0', selA => selA_sig, selB => selB_sig, mux_ctrl => sel_sig); end Behavioral;