-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:02:10 02/09/2016 -- Design Name: -- Module Name: C:/Users/Ajay Mittal/Documents/Xilinx/tey09022016/t09092/try0902.vhd -- Project Name: t09092 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: dct_FixPt -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY try0902 IS END try0902; ARCHITECTURE behavior OF try0902 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dct_FixPt PORT( clk : IN std_logic; x0 : IN std_logic_vector(15 downto 0); x1 : IN std_logic_vector(15 downto 0); x2 : IN std_logic_vector(15 downto 0); x3 : IN std_logic_vector(15 downto 0); x4 : IN std_logic_vector(15 downto 0); x5 : IN std_logic_vector(15 downto 0); x6 : IN std_logic_vector(15 downto 0); x7 : IN std_logic_vector(15 downto 0); f0 : OUT std_logic_vector(15 downto 0); f1 : OUT std_logic_vector(15 downto 0); f2 : OUT std_logic_vector(15 downto 0); f3 : OUT std_logic_vector(15 downto 0); f4 : OUT std_logic_vector(15 downto 0); f5 : OUT std_logic_vector(15 downto 0); f6 : OUT std_logic_vector(15 downto 0); f7 : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal x0 : std_logic_vector(15 downto 0) := (others => '0'); signal x1 : std_logic_vector(15 downto 0) := (others => '0'); signal x2 : std_logic_vector(15 downto 0) := (others => '0'); signal x3 : std_logic_vector(15 downto 0) := (others => '0'); signal x4 : std_logic_vector(15 downto 0) := (others => '0'); signal x5 : std_logic_vector(15 downto 0) := (others => '0'); signal x6 : std_logic_vector(15 downto 0) := (others => '0'); signal x7 : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal f0 : std_logic_vector(15 downto 0); signal f1 : std_logic_vector(15 downto 0); signal f2 : std_logic_vector(15 downto 0); signal f3 : std_logic_vector(15 downto 0); signal f4 : std_logic_vector(15 downto 0); signal f5 : std_logic_vector(15 downto 0); signal f6 : std_logic_vector(15 downto 0); signal f7 : std_logic_vector(15 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: dct_FixPt PORT MAP ( clk => clk, x0 => x0, x1 => x1, x2 => x2, x3 => x3, x4 => x4, x5 => x5, x6 => x6, x7 => x7, f0 => f0, f1 => f1, f2 => f2, f3 => f3, f4 => f4, f5 => f5, f6 => f6, f7 => f7 ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. --wait for 100 ns; x0<="0000000000000000"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000010"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000011"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000111"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000001"; x1<="0000000000000011"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000100"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000101"; x1<="0000000000000001"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; x0<="0000000000000000"; x1<="0000000000000011"; x2<="0000000000000010"; x3<="0000000000000011"; x4<="0000000000000100"; x5<="0000000000000101"; x6<="0000000000000110"; x7<="0000000000000111"; wait for clk_period; wait for clk_period*10; -- insert stimulus here wait; end process; END;