library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity reg is Generic (N : integer := 32); Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; ctrl0 : in STD_LOGIC; ctrl1 : in STD_LOGIC; ctrl2 : in STD_LOGIC; -- ctrl : in STD_LOGIC_VECTOR (2 downto 0); din : in STD_LOGIC_VECTOR (N-1 downto 0); dout : out STD_LOGIC_VECTOR (N-1 downto 0)); end reg; architecture reg_arch of reg is signal r_reg : STD_LOGIC_VECTOR (N-1 downto 0); signal r_next : STD_LOGIC_VECTOR (N-1 downto 0); begin process (clk, reset, ctrl0, ctrl1, ctrl2) begin if reset = '1' then r_reg <= (others => '0'); elsif clk'event and clk = '1' then if ctrl0 = '0' and ctrl1 ='0' and ctrl2 = '0' then r_reg <= din; elsif ctrl2 = '0' and ctrl1 = '0' and ctrl0 = '1' then -- Logic Left Shift r_reg <= din(N-2 downto 0) & '0'; elsif ctrl2 = '0' and ctrl1 = '1' and ctrl0 = '0' then -- Logic Right Shift r_reg <= '0' & din(N-1 downto 1); elsif ctrl2 = '0' and ctrl1 = '1' and ctrl0 = '1' then -- Arithmatic Left Shift r_reg <= din(N-2 downto 0) & '0'; elsif ctrl2 = '1' and ctrl1 = '0' and ctrl0 = '0' then -- Arithmatic Right Shift r_reg <= din(N-1) & din(N-1 downto 1); elsif ctrl2 = '1' and ctrl1 = '0' and ctrl0 = '1' then -- Barrel Left Shift r_reg <= din(N-2 downto 0) & din(N-1); elsif ctrl2 = '1' and ctrl1 = '1' and ctrl0 = '0' then -- Barrel Right Shift r_reg <= din(0) & din(N-1 downto 1); end if; end process; dout <= r_reg; end reg_arch;