-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:55:05 09/21/2015 -- Design Name: -- Module Name: C:/Projekte/FPGA/SimpleToggle/tb_wat.vhd -- Project Name: SimpleToggle -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: wat -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_wat IS END tb_wat; ARCHITECTURE behavior OF tb_wat IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT wat PORT( clk : IN std_logic; outb : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; --Outputs signal outb : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: wat PORT MAP ( clk => clk, outb => outb ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; END;