module PWM(output reg out_clk, input clk, input rst, input [7:0] thold ); reg [7:0] counter; always @(posedge clk) begin if(rst) begin counter <= 0; out_clk <= 0; end else begin counter <= counter + 1; if(counter < thold) begin out_clk <= 1; end else begin out_clk <= 0; end end end endmodule module Counter24(output reg [23:0] out, input clk, input rst ); always @(posedge clk) begin if(rst) out <= 0; else out <= out + 1; end endmodule module Decoder( input [2:0] in, output reg [7:0] out ); always @(*) case(in) 0: out = 8'b00000001; 1: out = 8'b00000010; 2: out = 8'b00000100; 3: out = 8'b00001000; 4: out = 8'b00010000; 5: out = 8'b00100000; 6: out = 8'b01000000; 7: out = 8'b10000000; endcase endmodule module UpDownCounter3( input clk, input rst, output reg [2:0] out ); reg dir; // 1 for up, 0 for down always @(posedge clk) if (rst) out<=0; else if(dir) out<=out+1; else out<=out-1; always @(*) if(out==7) dir=0; else if(out==0 && dir==0) dir=1; endmodule module Dec8(output [7:0] out, input [7:0] in ); assign out = in - 8'd64; endmodule module Transcodor( output reg [7:0] out, input [3:0] in ); always@(*) begin case (in[3:0]) // pabcdefg 4'd0: out[7:0] = 8'b10000001; 4'd1: out[7:0] = 8'b11001111; 4'd2: out[7:0] = 8'b10010010; 4'd3: out[7:0] = 8'b10000110; 4'd4: out[7:0] = 8'b11001100; 4'd5: out[7:0] = 8'b10100100; 4'd6: out[7:0] = 8'b10100000; 4'd7: out[7:0] = 8'b10001111; 4'd8: out[7:0] = 8'b10000000; 4'd9: out[7:0] = 8'b10000100; 4'hA: out[7:0] = 8'b10001000; 4'hB: out[7:0] = 8'b11100000; 4'hC: out[7:0] = 8'b10110001; 4'hD: out[7:0] = 8'b11000010; 4'hE: out[7:0] = 8'b10110000; 4'hF: out[7:0] = 8'b10111000; endcase end // always endmodule module Multiplexor( input [3:0] in1, input [3:0] in2, input [3:0] in3, input [3:0] in4, input [1:0] sel, output reg [3:0] out); always@(*) begin case(sel) 0: out = in1; 1: out = in2; 2: out = in3; 3: out = in4; endcase end endmodule