------------------------------------------------------------------------------------- -- Engineer: Nayan Patel -- -- Create Date: 02/01/2015 -- Design Name: spi_statemachine -- Module Name: spi_project/spi_statemachine.vhd -- Project Name: spi_project -- Target Device: DE0-Nano -- Tool versions: Quartus II 11.1sp2 -- Description: This is a state machine of the cores 'spi_master' and 'spi_slave' using -- the main ports only. -- -- VHDL State Machine Created by Nayan Patel for modules: 'spi_master', 'spi_slave', 'spi_instantiation' and 'spi_test' -- -- Dependencies: -- -- Revision: -- Additional Comments: -- -- Notes: ------------------------------------------------------------------------------------- library IEEE; -- Reference for VHDL source code use IEEE.STD_LOGIC_1164.all; -- Package defined in the IEEE (Found in library IEEE) use ieee.numeric_std.all; -- Used to covert integer to std_logic_vector via unsigned type -- Entity declaration entity spi_statemachine is generic (n: positive := 16; -- Number of bits cpol: std_logic := '0'; -- SPI mode selection (Mode 0 default) cpha: std_logic := '1'; -- CPOL = clock polarity and CPHA = clock phase prefetch: positive := 2; -- Prefetch lookahead cycles spi_2x_clk_div: positive := 5); -- For a 100MHz sclk_i, yields a 10MHz SCK port (-- Master -- di_m: out std_logic_vector(15 downto 0); wren_m: out std_logic; -- Slave -- do_s: in std_logic_vector(15 downto 0); do_valid_s: in std_logic; -- Start operation -- start: in std_logic; -- Clock operation -- rst_i: in std_logic; clk_i: in std_logic; -- Output indication -- correct: out std_logic); end spi_statemachine; -- Architecture behaviour architecture detect of spi_statemachine is -- Identifying the architecture type state_type is (createData, writeData, delay, writeEnable, checkValid, receivedData); -- Enumeration type signal state: state_type; -- State of the machine begin P1: process (clk_i, rst_i, do_o) -- Clock and reset variable dataLength: integer := 16; -- Length of data variable count: integer := 0; begin if rst_i = '0' then -- Reset operation used initialize all signals to predetermined state state <= createData; elsif clk_i'event and clk_i = '1' then -- Signal attribute used to test for a change on a signal case state is when createData => if (start = '1') then state <= writeData; else state <= createData; end if; when writeData => do_o <= do_s(dataLegnth); state <= delay; when delay => count := count + 1; if (count > 1) then state <= writeEnable; count := 0; else state <= delay; end if; when writeEnable => do_valid_o <= do_valid_s; state <= checkValid; when checkValid => state <= receivedData; when receivedData => if di_m = do_s then state <= checkFinished; end if; when others => null; end case; end if; end process; end detect;