LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.ALL; entity filt_decim is PORT( clk : IN std_logic; reset : IN std_logic; filter_in : IN std_logic_vector(7 DOWNTO 0); filter_out : OUT std_logic_vector( 19 DOWNTO 0) ); END filt_decim; architecture Beh of filt_decim is signal transfer : std_logic_vector ( 9 downto 0 ); signal clk_transfer : std_logic; component cic3r6 is PORT( clk : IN std_logic; reset : IN std_logic; x_in : IN std_logic_vector(7 DOWNTO 0); y_out : OUT std_logic_vector( 9 DOWNTO 0); clk2 : OUT std_logic ); end component; component fir is PORT( c : IN std_logic; r : IN std_logic; clk_enable : in std_logic; din : IN std_logic_vector(9 DOWNTO 0); dout : OUT std_logic_vector( 19 DOWNTO 0)); end component; begin q1:cic3r6 port map ( clk => clk, reset => reset, x_in => filter_in, y_out => transfer, clk2 => clk_transfer); q2:fir port map ( c => clk, clk_enable => clk_transfer, r => reset, din => transfer, dout => filter_out); end Beh; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_signed.ALL; ENTITY cic3r6 IS PORT ( clk, reset : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clk2 : OUT STD_LOGIC; y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END cic3r6; ARCHITECTURE fpga OF cic3r6 IS SUBTYPE word15 IS STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE STATE_TYPE IS (hold, sample); SIGNAL state : STATE_TYPE ; SIGNAL count : INTEGER RANGE 0 TO 5; SIGNAL x : STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '0'); SIGNAL sxtx : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL i0, i1 , i2 : word15 := (OTHERS=>'0'); SIGNAL i2d1, i2d2, c1, c0 : word15 := (OTHERS=>'0'); SIGNAL c1d1, c1d2, c2 : word15 := (OTHERS=>'0'); SIGNAL c2d1, c2d2, c3 : word15 := (OTHERS=>'0'); BEGIN FSM: PROCESS (reset, clk) BEGIN IF reset = '1' THEN state <= hold; count <= 0; clk2 <= '0'; ELSIF rising_edge(clk) THEN IF count = 5 THEN count <= 0; state <= sample; clk2 <= '1'; ELSE count <= count + 1; state <= hold; clk2 <= '0'; END IF; END IF; END PROCESS FSM; sx: PROCESS (x) BEGIN sxtx(7 DOWNTO 0) <= x; FOR k IN 15 DOWNTO 8 LOOP sxtx(k) <= x(x'high); END LOOP; END PROCESS sx; Int: PROCESS BEGIN WAIT UNTIL clk = '1'; x <= x_in; i0 <= i0 + sxtx; i1 <= i1 + i0 ; i2 <= i2 + i1 ; END PROCESS Int; Comb: PROCESS BEGIN WAIT UNTIL clk = '1'; IF state = sample THEN c0 <= i2; i2d1 <= c0; i2d2 <= i2d1; c1 <= c0 - i2d2; c1d1 <= c1; c1d2 <= c1d1; c2 <= c1 - c1d2; c2d1 <= c2; c2d2 <= c2d1; c3 <= c2 - c2d2; END IF; END PROCESS Comb; y_out <= c3(15 DOWNTO 6); END fpga; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fir is Port( din: in std_logic_vector(9 downto 0); dout: out std_logic_vector( 19 downto 0); clk_enable : in std_logic; r: in std_logic; c: in std_logic); end fir; architecture Behavioral of fir is constant h0 : std_logic_vector(9 downto 0) := "1111111001"; constant h1 : std_logic_vector(9 downto 0) := "0000011100"; constant h2 : std_logic_vector(9 downto 0) := "1111000000"; constant h3 : std_logic_vector(9 downto 0) := "0001100100"; constant h4 : std_logic_vector(9 downto 0) := "0110001100"; constant h5 : std_logic_vector(9 downto 0) := "0001100100"; constant h6 : std_logic_vector(9 downto 0) := "1111000000"; constant h7 : std_logic_vector(9 downto 0) := "0000011100"; constant h8 : std_logic_vector ( 9 downto 0 ) := "1111111001"; signal x0,x1,x2,x3,x4,x5,x6,x7,x8 : std_logic_vector ( 9 downto 0 ); signal m0,m1,m2,m3,m4,m5,m6,m7,m8 : std_logic_vector ( 19 downto 0 ); begin m0 <= signed(x0)*signed(h0); m1 <= signed(m0) + signed(x1)*signed(h1); m2 <= signed(m1) + signed(x2)*signed(h2); m3 <= signed(m2) + signed(x3)*signed(h3); m4 <= signed(m3) + signed(x4)*signed(h4); m5 <= signed(m4) + signed(x5)*signed(h5); m6 <= signed(m5) + signed(x6)*signed(h6); m7 <= signed(m6) + signed(x7)*signed(h7); m8 <= signed(m7) + signed(x8)*signed(h8); dout <= m8; process(c,r,clk_enable) begin if r = '1' then x0 <= (others => '0'); x1 <= (others => '0'); x2 <= (others => '0'); x3 <= (others => '0'); x4 <= (others => '0'); x5 <= (others => '0'); x6 <= (others => '0'); x7 <= (others => '0'); x8 <= (others => '0'); elsif (rising_edge(c) and clk_enable='1') then x0(9 downto 0) <= din(9 downto 0); x1(9 downto 0) <= x0(9 downto 0); x2(9 downto 0) <= x1(9 downto 0); x3(9 downto 0) <= x2(9 downto 0); x4(9 downto 0) <= x3(9 downto 0); x5(9 downto 0) <= x4(9 downto 0); x6(9 downto 0) <= x5(9 downto 0); x7(9 downto 0) <= x6(9 downto 0); x8(9 downto 0) <= x7(9 downto 0); end if; end process; end Behavioral;