module imageedge(bus,data_strobe, mode_strobe, bus_rw,clk, reset);

inout [7:0] bus;		// 'bus' is a bi-directional bus 


reg [7:0] bus_out;	// 8 bit internal register for storing output values 
wire [7:0] bus_in;	// this is used to get input data when 'bus' is acting as input. 

input data_strobe;	
input mode_strobe;	
...
input bus_rw;		// Indicates the direction of data on the data_bus. Pin1 READ=1 WRITE = 0 
input reset;		 
input clk;			

reg [7:0] row3 [33:0];	// 34 byte RAM 
reg [7:0] row2 [33:0];	// 34 byte RAM 
reg [7:0] row1 [33:0];	// 34 byte RAM 

reg [5:0] WAddr;		 
reg [5:0] RAddr;		// 6 bits to read 32 sobel outputs and future developments 
reg write_en,read_en;	 
reg [5:0] index;		
assign bus = (bus_rw)? bus_out : 8'dz;	// this code enables the duplexing of 'bus' 
assign bus_in = (!bus_rw) ? bus : 8'dz;	// -do- 
...
wire [7:0] out1;					
sobel s1(row1[0],row1[1],row1[2],
 row2[0],row2[2],
 row3[0],row3[1],row3[2],out1);
wire [7:0] out2;
sobel s2(row1[1],row1[2],row1[3],
 row2[1],row2[3],
...

begin
	if(!reset)						
	begin
		WAddr <= 6'b0;			 
		RAddr <= 6'b0;			
		read_en <= 1'b0;				 
		write_en <= 1'b0;				// this enables writing to FPGA 			 
		for(index=0;index<34;index=index+1)		// to avoid the don't care values. 
		row1[index] <= 8'b0;
		for(index=0;index<34;index=index+1)		// -do- 
		row2[index] <= 8'b0;
		bus_out <= 8'hff;			// to set bus_out reg value to FF 
	end

	else if(!data_strobe & !bus_rw & !write_en)	// condition for writing data to FPGA 
	begin
		row3[WAddr] <= bus_in;		// writes the data at bus_in to RAM location pointed by WAddr 
		WAddr <= WAddr + 1;		// setting write pointer to next location 
............

begin
		case (RAddr+1)			
			1: bus_out <= out1;	// this block will implement a 32:1 8 bit Vectored MUX 
			2: bus_out <= out2;
			3: bus_out <= out3;
			4: bus_out <= out4;
			5: bus_out <= out5;
			6: bus_out <= out6;
			7: bus_out <= out7;
			8: bus_out <= out8;
			9: bus_out <= out9;
			10: bus_out <= out10;
.......
endcase
		RAddr <= RAddr + 1;	// incrementing to next RAddr location. 
		read_en <= 1'b1;		// to ensure correct read operation 
	end

	else if(!mode_strobe & !bus_rw & !write_en)	// condition for indicating FPGA the end of one row 
	begin
		if(bus_in == 8'b0110_0110)	// '66' is code indicating end of row 
		begin
			for(index=0;index < 34;index = index + 1)	// this loop will implement row shift operation 
			begin
				row1[index] <= row2[index];
				row2[index] <= row3[index];
			end
			WAddr <= 6'b0;	
			RAddr <= 6'b0;
			write_en <= 1'b1;		// to ensure shifting is done only once.		 
		end
		bus_out <= 8'b0;
	end

	else if(data_strobe & mode_strobe)
	begin
else if(data_strobe & mode_strobe)
	begin
		write_en <= 1'b0;
		read_en <= 1'b0;			
	end
	else
	begin
		RAddr <= RAddr;
		WAddr <= WAddr;
		bus_out <= bus_out;
	end
end



endmodule



module sobel( p0, p1, p2, p3, p5, p6, p7, p8, out);

input  [7:0] p0,p1,p2,p3,p5,p6,p7,p8;	// 8 bit pixels inputs 
output [7:0] out;					// 8 bit output pixel 

wire signed [10:0] gx,gy;    //11 bits because max value of gx and gy is  
//255*4 and last bit for sign					 
wire signed [10:0] abs_gx,abs_gy;	 
wire [10:0] sum;			

//sobel mask for gradient in horiz. direction 
//sobel mask for gradient in vertical direction is done

assign abs_gx = (gx[10]? ~gx+1 : gx);	// to find the absolute value of gx. 
assign abs_gy = (gy[10]? ~gy+1 : gy);	// to find the absolute value of gy. 

assign sum = (abs_gx+abs_gy);				// finding the sum 
assign out = (|sum[10:8])?8'hff : sum[7:0];	// to limit the max value to 255  

endmodule