library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity ph_module is Port ( din : in STD_LOGIC_VECTOR (12 downto 0); r : in STD_LOGIC; c : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (25 downto 0)); end ph_module; architecture Behavioral of ph_module is signal sumsig : std_logic_vector ( 25 downto 0 ); signal sumsig1,sumsig2,sumsig3,sumsig4,sumsig5,sumsig6 : std_logic_vector ( 25 downto 0 ); signal commutator0,commutator1,commutator2,commutator3, commutator4,commutator5: std_logic_vector ( 12 downto 0 ); component subfilter1 port ( dins1 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts1 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter2 port ( dins2 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts2 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter3 port ( dins3 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts3 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter4 port ( dins4 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts4 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter5 port ( dins5 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts5 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter6 port ( dins6 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts6 : out STD_LOGIC_VECTOR (25 downto 0)); end component; begin commut: process(c) variable i : integer := 0; begin if (rising_edge(c)) then case i is when 0 => commutator5 <= din; when 1 => commutator4 <= din; when 2 => commutator3 <= din; when 3 => commutator2 <= din; when 4 => commutator1 <= din; when 5 => commutator0 <= din; when others => null; end case; if ( i < 6 ) then i := i + 1; else i := 0; sumsig <= signed(sumsig1) + signed(sumsig2) + signed(sumsig3) + signed(sumsig4) + signed(sumsig5) + signed(sumsig6); dout <= sumsig; end if; end if; end process commut; c1: subfilter1 port map ( dins1 => commutator0, douts1 => sumsig1, r => r, c => c ); c2: subfilter2 port map ( dins2 => commutator1, douts2 => sumsig2, r => r, c => c ); c3: subfilter3 port map ( dins3 => commutator2, douts3 => sumsig3, r => r, c => c ); c4: subfilter4 port map ( dins4 => commutator3, douts4 => sumsig4, r => r, c => c ); c5: subfilter5 port map ( dins5 => commutator4, douts5 => sumsig5, r => r, c => c ); c6: subfilter6 port map ( dins6 => commutator5, douts6 => sumsig6, r => r, c => c ); end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter1 is port ( dins1 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts1 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter1; architecture behavioral of subfilter1 is constant h10: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h11: std_logic_vector ( 12 downto 0 ) := "0000000000001"; constant h12: std_logic_vector ( 12 downto 0 ) := "0000000000001"; constant h13: std_logic_vector ( 12 downto 0 ) := "1111111110011"; constant h14: std_logic_vector ( 12 downto 0 ) := "0000000100000"; signal x10,x11,x12,x13,x14: std_logic_vector ( 12 downto 0 ); signal m10,m11,m12,m13,m14 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg1 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline1: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m10 <= signed(x10)*signed(h10); when 1 => m11 <= signed(m10) + signed(x11)*signed(h11); when 2 => m12 <= signed(m11) + signed(x12)*signed(h12); when 3 => m13 <= signed(m12) + signed(x13)*signed(h13); when 4 => m14 <= signed(m13) + signed(x14)*signed(h14); dout_reg1 <= m14; when others => null; end case; end loop; end if; end process pipeline1; fir1: process(r,c) begin if r='1' then x10 <= (others=>'0'); x11 <= (others=>'0'); x12 <= (others=>'0'); x13 <= (others=>'0'); x14 <= (others=>'0'); elsif (rising_edge(c)) then douts1 <= dout_reg1; x10( 12 downto 0 ) <= dins1( 12 downto 0 ); x11( 12 downto 0 ) <= x10( 12 downto 0 ); x12( 12 downto 0 ) <= x11( 12 downto 0 ); x13( 12 downto 0 ) <= x12( 12 downto 0 ); x14( 12 downto 0 ) <= x13( 12 downto 0 ); end if; end process fir1; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter2 is port ( dins2 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts2 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter2; architecture behavioral of subfilter2 is constant h20: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h21: std_logic_vector ( 12 downto 0 ) := "0000000000010"; constant h22: std_logic_vector ( 12 downto 0 ) := "1111111111111"; constant h23: std_logic_vector ( 12 downto 0 ) := "1111111110110"; constant h24: std_logic_vector ( 12 downto 0 ) := "0000000100100"; signal x20,x21,x22,x23,x24: std_logic_vector ( 12 downto 0 ); signal m20,m21,m22,m23,m24 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg2 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline2: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m20 <= signed(x20)*signed(h20); when 1 => m21 <= signed(m20) + signed(x21)*signed(h21); when 2 => m22 <= signed(m21) + signed(x22)*signed(h22); when 3 => m23 <= signed(m22) + signed(x23)*signed(h23); when 4 => m24 <= signed(m23) + signed(x24)*signed(h24); dout_reg2 <= m24; when others => null; end case; end loop; end if; end process pipeline2; fir2: process(r,c) begin if r='1' then x20 <= (others=>'0'); x21 <= (others=>'0'); x22 <= (others=>'0'); x23 <= (others=>'0'); x24 <= (others=>'0'); elsif (rising_edge(c)) then douts2 <= dout_reg2; x20( 12 downto 0 ) <= dins2( 12 downto 0 ); x21( 12 downto 0 ) <= x20( 12 downto 0 ); x22( 12 downto 0 ) <= x21( 12 downto 0 ); x23( 12 downto 0 ) <= x22( 12 downto 0 ); x24( 12 downto 0 ) <= x23( 12 downto 0 ); end if; end process fir2; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter3 is port ( dins3 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts3 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter3; architecture behavioral of subfilter3 is constant h30: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h31: std_logic_vector ( 12 downto 0 ) := "0000000000011"; constant h32: std_logic_vector ( 12 downto 0 ) := "1111111111011"; constant h33: std_logic_vector ( 12 downto 0 ) := "1111111111100"; constant h34: std_logic_vector ( 12 downto 0 ) := "0000000100010"; signal x30,x31,x32,x33,x34: std_logic_vector ( 12 downto 0 ); signal m30,m31,m32,m33,m34 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg3 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline3: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m30 <= signed(x30)*signed(h30); when 1 => m31 <= signed(m30) + signed(x31)*signed(h31); when 2 => m32 <= signed(m31) + signed(x32)*signed(h32); when 3 => m33 <= signed(m32) + signed(x33)*signed(h33); when 4 => m34 <= signed(m33) + signed(x34)*signed(h34); dout_reg3 <= m34; when others => null; end case; end loop; end if; end process pipeline3; fir3: process(r,c) begin if r='1' then x30 <= (others=>'0'); x31 <= (others=>'0'); x32 <= (others=>'0'); x33 <= (others=>'0'); x34 <= (others=>'0'); elsif (rising_edge(c)) then douts3 <= dout_reg3; x30( 12 downto 0 ) <= dins3( 12 downto 0 ); x31( 12 downto 0 ) <= x30( 12 downto 0 ); x32( 12 downto 0 ) <= x31( 12 downto 0 ); x33( 12 downto 0 ) <= x32( 12 downto 0 ); x34( 12 downto 0 ) <= x33( 12 downto 0 ); end if; end process fir3; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter4 is port ( dins4 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts4 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter4; architecture behavioral of subfilter4 is constant h40: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h41: std_logic_vector ( 12 downto 0 ) := "0000000000011"; constant h42: std_logic_vector ( 12 downto 0 ) := "1111111111000"; constant h43: std_logic_vector ( 12 downto 0 ) := "0000000000100"; constant h44: std_logic_vector ( 12 downto 0 ) := "0000000011010"; signal x40,x41,x42,x43,x44: std_logic_vector ( 12 downto 0 ); signal m40,m41,m42,m43,m44 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg4 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline4: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m40 <= signed(x40)*signed(h40); when 1 => m41 <= signed(m40) + signed(x41)*signed(h41); when 2 => m42 <= signed(m41) + signed(x42)*signed(h42); when 3 => m43 <= signed(m42) + signed(x43)*signed(h43); when 4 => m44 <= signed(m43) + signed(x44)*signed(h44); dout_reg4 <= m44; when others => null; end case; end loop; end if; end process pipeline4; fir4: process(r,c) begin if r='1' then x40 <= (others=>'0'); x41 <= (others=>'0'); x42 <= (others=>'0'); x43 <= (others=>'0'); x44 <= (others=>'0'); elsif (rising_edge(c)) then douts4 <= dout_reg4; x40( 12 downto 0 ) <= dins4( 12 downto 0 ); x41( 12 downto 0 ) <= x40( 12 downto 0 ); x42( 12 downto 0 ) <= x41( 12 downto 0 ); x43( 12 downto 0 ) <= x42( 12 downto 0 ); x44( 12 downto 0 ) <= x43( 12 downto 0 ); end if; end process fir4; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter5 is port ( dins5 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts5 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter5; architecture behavioral of subfilter5 is constant h50: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h51: std_logic_vector ( 12 downto 0 ) := "0000000000011"; constant h52: std_logic_vector ( 12 downto 0 ) := "1111111110101"; constant h53: std_logic_vector ( 12 downto 0 ) := "0000000001110"; constant h54: std_logic_vector ( 12 downto 0 ) := "0000000001010"; signal x50,x51,x52,x53,x54: std_logic_vector ( 12 downto 0 ); signal m50,m51,m52,m53,m54: std_logic_vector ( 25 downto 0 ) ; signal dout_reg5 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline5: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m50 <= signed(x50)*signed(h50); when 1 => m51 <= signed(m50) + signed(x51)*signed(h51); when 2 => m52 <= signed(m51) + signed(x52)*signed(h52); when 3 => m53 <= signed(m52) + signed(x53)*signed(h53); when 4 => m54 <= signed(m53) + signed(x54)*signed(h54); dout_reg5 <= m54; when others => null; end case; end loop; end if; end process pipeline5; fir5: process(r,c) begin if r='1' then x50 <= (others=>'0'); x51 <= (others=>'0'); x52 <= (others=>'0'); x53 <= (others=>'0'); x54 <= (others=>'0'); elsif (rising_edge(c)) then douts5 <= dout_reg5; x50( 12 downto 0 ) <= dins5( 12 downto 0 ); x51( 12 downto 0 ) <= x50( 12 downto 0 ); x52( 12 downto 0 ) <= x51( 12 downto 0 ); x53( 12 downto 0 ) <= x52( 12 downto 0 ); x54( 12 downto 0 ) <= x53( 12 downto 0 ); end if; end process fir5; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter6 is port ( dins6 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts6 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter6; architecture behavioral of subfilter6 is constant h60: std_logic_vector ( 12 downto 0 ) := "0000000000000"; constant h61: std_logic_vector ( 12 downto 0 ) := "0000000000011"; constant h62: std_logic_vector ( 12 downto 0 ) := "1111111110011"; constant h63: std_logic_vector ( 12 downto 0 ) := "0000000011000"; constant h64: std_logic_vector ( 12 downto 0 ) := "1111111110101"; signal x60,x61,x62,x63,x64: std_logic_vector ( 12 downto 0 ); signal m60,m61,m62,m63,m64: std_logic_vector ( 25 downto 0 ) ; signal dout_reg6 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline6: process(c) begin if ( rising_edge(c) ) then for i in 0 to 4 loop case i is when 0 => m60 <= signed(x60)*signed(h60); when 1 => m61 <= signed(m60) + signed(x61)*signed(h61); when 2 => m62 <= signed(m61) + signed(x62)*signed(h62); when 3 => m63 <= signed(m62) + signed(x63)*signed(h63); when 4 => m64 <= signed(m63) + signed(x64)*signed(h64); dout_reg6 <= m64; when others => null; end case; end loop; end if; end process pipeline6; fir6: process(r,c) begin if r='1' then x60 <= (others=>'0'); x61 <= (others=>'0'); x62 <= (others=>'0'); x63 <= (others=>'0'); x64 <= (others=>'0'); elsif (rising_edge(c)) then douts6 <= dout_reg6; x60( 12 downto 0 ) <= dins6( 12 downto 0 ); x61( 12 downto 0 ) <= x60( 12 downto 0 ); x62( 12 downto 0 ) <= x61( 12 downto 0 ); x63( 12 downto 0 ) <= x62( 12 downto 0 ); x64( 12 downto 0 ) <= x63( 12 downto 0 ); end if; end process fir6; end behavioral;