package body
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--      Package File Template
--
--      Purpose: This package defines supplemental types, subtypes,
--               constants, and functions


library IEEE;
use IEEE.STD_LOGIC_1164.all;

package pack_puf is


  constant m : integer :=3;
   type row_bit is array (m downto 0) of bit;

end pack_puf;
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main body
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-- Company:
-- Engineer:
--
-- Create Date:    20:30:06 09/30/2014
-- Design Name:
-- Module Name:    cascaded_puf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.pack_puf.all;
use IEEE.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cascaded_puf is

   generic(lngth:integer:=3);
            Port ( I,J : in  bit;
           C : in  row_bit;
           P,Q : out  bit);

end cascaded_puf;

architecture Behavioral of cascaded_puf is

begin
  process(C)
    variable temp1:row_bit;
         variable temp2:row_bit;
  begin
       if(C(0)='0') then
                        temp1(0):=I;
                        temp2(0):=j;
                 else
         temp1(0):=J;
                        temp2(0):=I;
                 end if;
                     for i in 1 to lngth loop
                              if(C(i)='0') then
                                          temp1(i):=temp1(i-1);
                                                temp2(i):=temp2(i-1);
                         else
                                           temp1(i):=temp2(i-1);
                                           temp2(i):=temp1(i-1);
                                        end if;
                          end loop;
                          P <= temp1(lngth);
                          Q <= temp2(lngth);
    end process;
end Behavioral;

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