library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity validade is port(validBitIn: in std_logic; validTag1, validTag2: in std_logic_vector(3 downto 0); validOut: out std_logic); end entity; architecture comportamental of validade is begin process(validBitIn,validTag1,validTag2) begin validOut<=(validTag1(0) xnor validTag2(0)) and (validTag1(1) xnor validTag2(1)) and (validTag1(2) xnor validTag2(2)) and (validTag1(3) xnor validTag2(3)) and validBitIn; end process; end comportamental;