library ieee; use ieee.std_logic_1164.all; entity demux1x4 is Port (demuxIn: In std_logic_vector (15 downto 0); demuxControl: In std_logic_vector (1 downto 0); demuxOut0, demuxOut1, demuxOut2, demuxOut3: Out std_logic_vector (15 downto 0)); end demux1x4; architecture comportamental of demux1x4 is CONSTANT Z:std_logic_vector (15 downto 0):="ZZZZZZZZZZZZZZZZ"; begin process(demuxControl,demuxIn) begin case demuxControl is when "00" => demuxOut0<=demuxIn; demuxOut1<=Z; demuxOut2<=Z; demuxOut3<=Z; when "01" => demuxOut1<=demuxIn; demuxOut0<=Z; demuxOut2<=Z; demuxOut3<=Z; when "10" => demuxOut2<=demuxIn; demuxOut0<=Z; demuxOut1<=Z; demuxOut3<=Z; when "11" => demuxOut3<=demuxIn; demuxOut0<=Z; demuxOut1<=Z; demuxOut2<=Z; when others => demuxOut3<=Z; demuxOut0<=Z; demuxOut1<=Z; demuxOut2<=Z; end case; end process; end comportamental;